Senior High-Speed Analog/Mixed-Signal Design Engineer

Nokia Corporation; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Nokia Corporation in San Jose, CA seeks a Principal Design Engineer to design, analyze, and bring high-speed analog/mixed-signal circuits to production using advanced CMOS FinFET technologies. You will optimize ADCs, DACs, PLLs, and related IPs, while drafting floor plans and guiding layout teams to achieve performance goals.

The role requires deep knowledge of Cadence tools, device physics, and Verilog-AMS modeling, with a track record of delivering complex analog/mixed-signal designs to

Qualifications

• MS in E.E. with 12+ years' experience or Ph.D. in E.E. with 8+ years' experience
• Experience designing analog/mixed-signal IPs or chips in deep submicron CMOS technologies
• Experience bringing high-speed ADC, DAC, and PLL to production
• Solid understanding of CMOS analog/mixed signal design methodologies and device physics
• Ability to perform behavioral modeling with Verilog-A/Verilog-AMS
• Collaborative with cross-functional teams in fast-paced environments

Responsibilities

• Design, implement, and simulate high-speed analog circuits including ADCs, DACs
• Create layout floor plans and supervise layout engineers; hands-on in drawing layout if needed
• Evaluate topology trade-offs to meet power/area/linearity/bandwidth targets
• Develop analog test plans and characterize products with PE/TE teams
• Support adherence to design methodologies and release flows

Skills

Analog/mixed-signal design

CMOS device physics

CMOS design methodologies

Verilog-A / Verilog-AMS

Cross-functional collaboration

Education

MS in EE (12+ years)

PhD in EE (8+ years)

Tools

Cadence Virtuoso

Spectre

Incisive

Calibre

EMX

Totem EM/IR

Job description

Nokia Corporation in San Jose, CA seeks a Principal Design Engineer to design, analyze, and bring high-speed analog/mixed-signal circuits to production using advanced CMOS FinFET technologies. You will optimize ADCs, DACs, PLLs, and related IPs, while drafting floor plans and guiding layout teams to achieve performance goals.

The role requires deep knowledge of Cadence tools, device physics, and Verilog-AMS modeling, with a track record of delivering complex analog/mixed-signal designs to