Senior High-Speed Analog Layout Engineer for AI Chips

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Foundational role

Cross-functional teams

International team culture

Growth with Celero

AI and data center connectivity

Job summary

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive the layout of analog/mixed-signal IP blocks for high-performance optical communication systems.

You will collaborate with circuit designers, CAD/PDK teams, and layout engineers across time zones, mentoring others and ensuring first-pass silicon success. The role demands hands-on expertise and strong communication.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout design in advanced CMOS/FinFET technologies.
• Leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred).
• Experience with TSMC FinFET nodes (N3, N5, N7, or N16).
• Expertise in device physics, layout-dependent effects, and parasitic minimization.
• Proficiency with Cadence Virtuoso, Calibre, Pegasus, and signoff flows (LVS, DRC, PERC).
• Experience collaborating with international and remote teams.

Responsibilities

• Lead the physical layout design of complex analog/mixed-signal macros from floor planning through verification.
• Collaborate with schematic designers to optimize layouts for performance, matching, symmetry, and reliability.
• Mentor junior layout engineers across multiple time zones, enforcing best practices.
• Perform and debug LVS, DRC, PERC, ERC, and other signoff checks with industry tools.
• Contribute to chip-level planning including top-level floor planning and block integration.
• Participate in layout design reviews and drive layout quality, verification, and schedule adherence.
• Support automation through scripting (SKILL, TCL, Python).

Skills

Leadership

Mentoring

Communication

Problem-solving

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC tooling

SKILL

Python

Job description

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive the layout of analog/mixed-signal IP blocks for high-performance optical communication systems.

You will collaborate with circuit designers, CAD/PDK teams, and layout engineers across time zones, mentoring others and ensuring first-pass silicon success. The role demands hands-on expertise and strong communication.