Senior High-Speed Analog IC Layout Architect

eInfochips (An Arrow Company); Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

eInfochips (An Arrow Company) is hiring a High-Speed Analog Layout Engineer to design physical silicon layouts for high-frequency mixed-signal circuits such as SerDes, ADCs, DACs, and PLLs. You will lead floor planning, manage hierarchical integration, and address parasitic and noise challenges.

The role requires 5–12+ years of hands-on custom IC layout experience, with critical exposure to lower nodes (N3, N5). This is an onsite position with potential travel to Arrow client locations as needed.

Qualifications

• Reliability & Verification: Ensure complete closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
• 5–12+ years of hands-on custom IC layout experience.
• Experience at Lower node (N3, N5) is critical for this position.

Responsibilities

• Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design.
• Parasitic & Noise Control: Address LOD, WPE, LDE, device matching, guard rings, and isolation or shielding (coaxial, differential, ground shields).
• Must be able to travel to Arrow Client offices; onsite work arrangement.

Skills

Custom IC layout

Layout verification

High-speed/analog layout

Sub-micron CMOS/FinFET experience

Job description

eInfochips (An Arrow Company) is hiring a High-Speed Analog Layout Engineer to design physical silicon layouts for high-frequency mixed-signal circuits such as SerDes, ADCs, DACs, and PLLs. You will lead floor planning, manage hierarchical integration, and address parasitic and noise challenges.

The role requires 5–12+ years of hands-on custom IC layout experience, with critical exposure to lower nodes (N3, N5). This is an onsite position with potential travel to Arrow client locations as needed.