Principal High-Speed Analog Layout Architect

Socket.dev; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Foundational startup role

International team culture

Growth opportunities

Job summary

Socket.dev seeks a Senior/Principal Analog Layout Engineer to drive layout for analog/mixed-signal IP blocks in advanced optical systems. You will lead layout for ADCs, DACs, PLLs and high-performance circuits, partnering with circuit designers and CAD/PDK teams.

This hands-on role includes mentoring, LVS/DRC/PERC checks, floor planning, power grid work, and routing, with Cadence Virtuoso, Calibre, Pegasus, and scripting skills a plus. Irvine or San Jose based in CA.

Qualifications

• 10+ years of analog/mixed-signal layout in CMOS/FinFET tech.
• Proven IP/layout macro ownership and handoff to Physical Design.
• Leadership in owning major IP layout macros or full-chip layouts.
• At least 1 year with TSMC FinFET nodes (N3/N5/N7/N16).
• Deep understanding of LOD, WPE, OSE, LDE and related effects.
• Expertise in device matching, noise isolation, ESD, symmetry, parasitics.
• Floor planning, hierarchical integration, routing, power/ground design.
• Cadence Virtuoso, Calibre, Pegasus; LVS/DRC/verification flows.
• Collaborative with international/remote teams; strong documentation.

Responsibilities

• Lead physical layout of analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers for optimum layout performance and matching.
• Mentor junior layout engineers across multiple time zones.
• Perform LVS, DRC, PERC, ERC and other signoff checks.
• Contribute to chip-level planning: top-level floor planning and power grid.
• Lead layout review sessions; ensure quality and schedule adherence.
• Support automation via scripting (SKILL, TCL, Python).

Skills

Analog/mixed-signal layout

Leadership

Mentoring

Layout verification

LVS/DRC/PERC

Floor planning

Routing and placement

Scripting (Python, TCL, SKILL)

Documentation

Cross-functional collaboration

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC tools

SKILL

TCL

Python

Job description

Socket.dev seeks a Senior/Principal Analog Layout Engineer to drive layout for analog/mixed-signal IP blocks in advanced optical systems. You will lead layout for ADCs, DACs, PLLs and high-performance circuits, partnering with circuit designers and CAD/PDK teams.

This hands-on role includes mentoring, LVS/DRC/PERC checks, floor planning, power grid work, and routing, with Cadence Virtuoso, Calibre, Pegasus, and scripting skills a plus. Irvine or San Jose based in CA.