Senior High-Speed Analog IC Layout Engineer

Saige Partners; California (MO); On-site; USD 140,000 - 210,000; Full time

Job summary

Saige Partners in San Jose, CA is seeking a Senior High-Speed Mixed-Signal / Analog IC Layout Engineer to lead analog layout of high-speed transceiver blocks and support design teams.

Ideal candidate has 5+ years in deep sub-micron/FinFET analog layout, expertise in floor planning, device structures, and parasitics, with Cadence Virtuoso and Mentor Calibre proficiency.

You will collaborate across disciplines to ensure signal integrity and power integrity while meeting tight schedules.

Qualifications

• Associate degree or higher with formal training in custom analog layout.
• 5 years analog layout experience in deep sub-micron and FinFET processes.
• Experience in floor planning and layout of analog blocks such as amplifiers, drivers, LDO, PLL, filters.
• Solid knowledge of device structures.
• Understanding tradeoffs in matching, coupling, parasitic effects and area.
• Understanding causes and preventions of ESD and latch-up.
• Proficient in interpreting verification DRC, LVS, ERC, ANT results.
• Working knowledge of Cadence Virtuoso and Mentor Calibre.
• Team player with excellent communication skills.

Responsibilities

• Layout of Analog / High Speed transceiver circuit blocks in a timely manner.
• Layout of sensitive active / passive components including resistors, capacitors and inductors.
• Design verification including DRC, LVS, ERC and ANT and extraction.
• Block level floor planning with design engineers.
• Review and update layout for quality including signal integrity, power integrity and parasitic.

Skills

Analog layout

Floor planning

Device structures

Parasitics awareness

Communication

Team collaboration

Education

Associate degree or above in electronics

BSEE or above

Tools

Cadence Virtuoso

Mentor Calibre

Job description

Saige Partners in San Jose, CA is seeking a Senior High-Speed Mixed-Signal / Analog IC Layout Engineer to lead analog layout of high-speed transceiver blocks and support design teams.

Ideal candidate has 5+ years in deep sub-micron/FinFET analog layout, expertise in floor planning, device structures, and parasitics, with Cadence Virtuoso and Mentor Calibre proficiency.

You will collaborate across disciplines to ensure signal integrity and power integrity while meeting tight schedules.