Lead Analog Layout Architect – High-Speed IP

Celero Communications, Inc.; Irvine (CA); Presencial; USD 180 000 - 270 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

High-growth startup

Cross-functional teams

International team

Growth opportunity

Resumo da oferta

Celero Communications, Inc. is a fast-growing semiconductor startup in Irvine, CA seeking a Principal/Senior Analog Layout Engineer to lead complex layout of ADCs, DACs, PLLs, and other high‑performance blocks.

You will mentor international teammates, drive layout quality, and partner with CAD/PDK teams to ensure first-pass silicon success. The role emphasizes hands-on design, floor planning, power grid, and rigorous signoff checks using LVS/DRC/PEC/ERC, with scripting for automation.

Qualificações

• 10+ years of hands-on analog/mixed-signal layout in advanced CMOS/FinFET tech.
• Proven IP layout macro or full-chip layout leadership at FinFET nodes.
• Experience with TSMC FinFET nodes (N3/N5/N7/N16).
• Deep understanding of LOD, WPE, OSE, LDE and related effects.
• Experience with layout verification flows (LVS/DRC/PERC/ERC).

Responsabilidades

• Lead physical layout of analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers to optimize layout for performance and matching.
• Mentor junior layout engineers and contractors across time zones.
• Perform LVS, DRC, PERC, ERC checks and signoff reports.
• Contribute to top-level floor planning and power grid design.
• Lead layout design reviews and ensure schedule adherence.
• Support automation through scripting (SKILL, TCL, Python).

Conhecimentos

Analog layout

Mixed-signal layout

Leadership

Schematic collaboration

Cadence Virtuoso

Calibre

LVS/DRC/PEC

Python scripting

Ferramentas

Cadence Virtuoso

Calibre

Pegasus

Descrição da oferta de emprego

Celero Communications, Inc. is a fast-growing semiconductor startup in Irvine, CA seeking a Principal/Senior Analog Layout Engineer to lead complex layout of ADCs, DACs, PLLs, and other high‑performance blocks.

You will mentor international teammates, drive layout quality, and partner with CAD/PDK teams to ensure first-pass silicon success. The role emphasizes hands-on design, floor planning, power grid, and rigorous signoff checks using LVS/DRC/PEC/ERC, with scripting for automation.