Senior Analog Design Engineer

eInfochips (An Arrow Company); Austin (TX); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

eInfochips (An Arrow Company) is hiring a High-Speed Analog Layout Engineer to design physical silicon layouts for high-frequency mixed-signal circuits such as SerDes, ADCs, DACs, and PLLs. You will lead floor planning, manage hierarchical integration, and address parasitic and noise challenges.

The role requires 5–12+ years of hands-on custom IC layout experience, with critical exposure to lower nodes (N3, N5). This is an onsite position with potential travel to Arrow client locations as needed.

Qualifications

• Reliability & Verification: Ensure complete closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
• 5–12+ years of hands-on custom IC layout experience.
• Experience at Lower node (N3, N5) is critical for this position.

Responsabilités

• Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design.
• Parasitic & Noise Control: Address LOD, WPE, LDE, device matching, guard rings, and isolation or shielding (coaxial, differential, ground shields).
• Must be able to travel to Arrow Client offices; onsite work arrangement.

Connaissances

Custom IC layout

Layout verification

High-speed/analog layout

Sub-micron CMOS/FinFET experience

Description du poste

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Responsibilities

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design.

Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields).

What We Are Looking For:

• Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
• Generally 5 to 12+ years of hands‑on custom IC layout experience in deep sub‑micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
• Experience at Lower node (N3, N5) is critical for this position.

Work Arrangement Fully Onsite:

Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

About eInfochips:

eInfochips, an Arrow company (Fortune#154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across

various industries & verticals.

Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries C verticals.

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.