Senior Security Verification Engineer

Analog Devices; Wilmington (MA); On-site; USD 110,385 - 151,808; Full time

Benefits offered by this job

Discretionary bonus

Medical coverage

Vision & dental

Job summary

Analog Devices, Inc. in the United States is seeking a highly motivated Senior Design Verification Engineer to join our Security IP team developing next-generation hardware security solutions.

You will own verification efforts for complex security IP and subsystem designs, working with design, architecture, firmware, and validation teams to ensure robust functionality, security, and quality. The role involves developing advanced verification environments, driving coverage closure, debugging

Qualifications

• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Typically 4–7 years of experience in digital design verification.
• Strong proficiency in System Verilog and UVM methodology.
• Experience developing reusable verification environments, scoreboards, checkers, and coverage models.
• Strong understanding of verification concepts including: Constrained-random verification; Functional coverage; Assertion-Based Verification (SVA); Regression management; Coverage closure.
• Experience with RTL simulation and debug tools (e.g., VCS, Xcelium, Simvision, Verdi, Questa).
• Strong analytical and debugging skills with demonstrated ability to independently solve complex verification challenges.
• Experience with scripting languages such as Python, Perl, or Tcl.
• Experience doing System on Chip (SoC) verification involving writing C test cases.
• Experience working in Linux environments
• Experience verifying processor-based systems such as ARM Cortex-M, RISC-V, or similar embedded processors.
• Experience with common SoC interfaces such as APB, AHB, AXI, QSPI, UART, and DMA architectures.

Responsibilities

• Own block-level and subsystem-level verification activities for security-focused IPs and secure enclave solutions.
• Develop comprehensive verification plans based on architecture specifications, threat models, and product requirements.
• Create, enhance, and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, assertions, and functional coverage models.
• Develop constrained-random and directed test scenarios targeting functional, security, and corner-case behaviors.
• Drive verification closure through code coverage, functional coverage, assertion coverage, and regression analysis.
• Collaborate with RTL designers, architects, firmware engineers, and security experts to understand design intent and security requirements.
• Debug complex RTL and simulation failures, perform root-cause analysis, and drive issue resolution.
• Verify processor-based subsystems writing C tests, hardware cryptographic accelerators, secure boot mechanisms, key management functions, and security controllers.
• Support emulation, firmware integration, and post-silicon validation activities.
• Contribute to reusable VIP, automation infrastructure, and verification methodology improvements across the organization.
• Mentor junior verification engineers and provide technical guidance on verification best practices.

Skills

SystemVerilog

UVM

Verification environments

Python

C tests

Linux

SoC verification

ARM Cortex-M/RISC-V

APB/AHB/AXI interfaces

RTL simulation

Education

Bachelor's or Master’s in Electrical Engineering, Computer Engineering, Computer Science

Tools

VCS

Xcelium

Simvision

Verdi

Questa

Job description

Analog Devices, Inc. in the United States is seeking a highly motivated Senior Design Verification Engineer to join our Security IP team developing next-generation hardware security solutions.

You will own verification efforts for complex security IP and subsystem designs, working with design, architecture, firmware, and validation teams to ensure robust functionality, security, and quality. The role involves developing advanced verification environments, driving coverage closure, debugging