Senior FPGA/SoC Engineer for Space Missions

Anduril Industries; Costa Mesa (CA); On-site; USD 167,000 - 222,000; Full time

Benefits offered by this job

Equity grants

Comprehensive benefits

Job summary

Anduril Industries in Costa Mesa, CA is seeking a Sr. FPGA/SoC Engineer to develop firmware for FPGA/SoC designs and oversee third-party development.

You will collaborate with internal and external teams to architect, write RTL (VHDL/Verilog), and debug across the design life cycle, including bring-up on ARM-based systems and high-speed interfaces. A US Secret clearance eligibility is required, with 5 years of FPGA experience preferred.

Qualifications

• 5 years of FPGA/HDL hardware design experience, with Xilinx Versal SoC preferred.
• Proficient in VHDL and/or Verilog; Vivado/ModelSim/Quartus experience.
• Eligible to obtain and maintain an active U.S. Secret security clearance.
• Experience in SoC hardware bring-up, preferably on ARM-based systems.

Responsibilities

• Rapidly develop, test, and implement FPGA designs using Xilinx SoC/FPGA.
• Integrate third-party vendors IP as necessary.
• Work with third-party developers to ensure timely product success.
• Perform digital circuit design, VHDL/Verilog coding, synthesis, place and route, timing closure, simulation, and verification.
• Participate in entire design life cycle: from requirements and concept to design and board bring-up.
• Implement high-speed communications (ethernet, serial) and signal processing (analog, digital).
• Ensure designs meet safety and performance standards with traceability to top-level requirements.
• Investigate and resolve bugs at HDL and system level.

Skills

FPGA/HDL hardware design

VHDL/Verilog coding

Problem-solving

Teamwork

Security clearance

Tools

Vivado

ModelSim

Quartus

Job description

Anduril Industries in Costa Mesa, CA is seeking a Sr. FPGA/SoC Engineer to develop firmware for FPGA/SoC designs and oversee third-party development.

You will collaborate with internal and external teams to architect, write RTL (VHDL/Verilog), and debug across the design life cycle, including bring-up on ARM-based systems and high-speed interfaces. A US Secret clearance eligibility is required, with 5 years of FPGA experience preferred.