Senior FPGA Silicon Design Engineer

191 Altera Corporation; San Jose (CA); On-site; USD 149,000 - 213,000; Full time

Job summary

Altera is seeking an FPGA Silicon Design Engineer to contribute to design, verification, implementation, and silicon bring-up of next‑gen FPGA devices. You will develop complex digital logic and RTL while supporting the full ASIC flow from synthesis to physical design and timing closure.

The ideal candidate has strong digital design expertise with backend ASIC physical design experience and a disciplined approach to execution.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 8+ years of FPGA/ASIC design experience.
• Must be authorized to work in the United States without employer-sponsored immigration support for this position.
• 5+ years designing complex digital logic and RTL with Verilog and/or SystemVerilog.
• 5+ years backend ASIC physical design experience: synthesis, floorplanning, placement, clock-tree synthesis, routing, timing/power analysis.
• 5+ years using industry-standards EDA tools such as Synopsys, Cadence, Siemens, or equivalent.
• 5+ years experience in clock-domain crossing, reset architecture, and low-power techniques.
• 5+ years of SystemVerilog/UVM verification, simulation, and coverage-based debug.
• 5+ years scripting in Python, Perl, Tcl, or Shell in Unix/Linux.
• 5+ years debugging design issues with cross-functional teams.
• Excellent communication and design-review skills.

Responsibilities

• Architect, design, and implement complex digital logic for FPGA silicon.
• Develop production-quality RTL using Verilog and SystemVerilog.
• Define and execute design verification plans using UVM and SystemVerilog assertions.
• Execute backend ASIC physical design: synthesis, floorplanning, placement, clocking, routing.
• Analyze PPA and optimize to meet product targets.
• Collaborate with architecture, verification, physical design, software, firmware, and product teams.
• Contribute to silicon bring-up, post-silicon debug, and characterization.
• Develop and maintain design specs, architecture docs, and verification plans.
• Participate in design/code reviews and communicate risks and trade-offs.

Skills

Verilog

SystemVerilog

UVM

RTL design

Python scripting

Digital logic

Back-end ASIC physical design

Clock-domain crossing

Debugging & root-cause analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Master's or Ph.D. degree (preferred)

Tools

Synopsys tools

Cadence tools

Siemens tools

Industry-standard EDA tools

Job description

Altera is seeking an FPGA Silicon Design Engineer to contribute to design, verification, implementation, and silicon bring-up of next‑gen FPGA devices. You will develop complex digital logic and RTL while supporting the full ASIC flow from synthesis to physical design and timing closure.

The ideal candidate has strong digital design expertise with backend ASIC physical design experience and a disciplined approach to execution.