Senior FPGA/RTL Design Engineer - MIMO Signal Processing

Silvus; Irvine (CA); Hybrid; USD 125,000 - 195,000; Full time

Job summary

Silvus is seeking a Senior FPGA/RTL Design Engineer to join our team in Irvine, CA. This role involves participating in the research and development process for innovative communication products using advanced FPGA technology.

The ideal candidate will have extensive experience in FPGA design, including skills in digital signal processing and familiarity with Xilinx FPGAs. This position supports a hybrid work model, emphasizing a collaborative environment promoting the development of cutting-edge communication solutions.

Qualifications

• 6+ years of experience in FPGA design; or 4 years with a Master's degree.
• Experience with fixed point arithmetic and digital signal processing.
• Familiarity with logic analyzers and hardware verification.

Responsibilities

• Digital design architecting for wireless communication projects.
• Design of signal processing blocks working with systems engineers.
• RTL coding, simulation, and FPGA synthesis testing.

Skills

FPGA design

Digital signal processing

Xilinx FPGAs

MATLAB

Education

Bachelor of Science in Electrical Engineering or Computer Science

Master of Science in Electrical Engineering

Tools

Vivado IDE

Job description

Silvus is seeking a Senior FPGA/RTL Design Engineer to join our team in Irvine, CA. This role involves participating in the research and development process for innovative communication products using advanced FPGA technology.

The ideal candidate will have extensive experience in FPGA design, including skills in digital signal processing and familiarity with Xilinx FPGAs. This position supports a hybrid work model, emphasizing a collaborative environment promoting the development of cutting-edge communication solutions.