Senior FPGA & RTL Signal Processing Engineer

Motorola Solutions; Los Angeles (CA); Hybrid; USD 125,000 - 195,000; Full time

Benefits offered by this job

Bonus plans

Medical, Dental, Vision

401(k) with company match

Paid holidays

Generous paid time off

Employee stock purchase plan

Parental & family leave

Job summary

Motorola Solutions, via its Silvus Technologies subsidiary, seeks a Senior FPGA Design Engineer focused on signal processing in a West Los Angeles setting. Hybrid role requiring at least three onsite days per week.

The engineer will drive RTL development, DSP, and fixed-point implementations for high-performance wireless projects. Ideal candidates have 6+ years FPGA experience (or 4 with a Master, 2 with a PhD), Xilinx/Vivado expertise, and the ability to work across clock domains with strong

Qualifications

• Bachelor degree in Electrical Engineering or related field.
• Minimum 6 years FPGA design experience or 4 years with a Master’s or 2 with a Ph.D.
• Experience with fixed-point arithmetic and DSP designs.
• Proven high-utilization, multi clock-domain FPGA designs.
• Experience with Xilinx FPGAs/SoCs and Vivado IDE.
• U.S. Person status required and background/drug screening completed.

Responsibilities

• Architect digital designs for wireless/communication projects.
• Develop RTL code, simulate, and build test benches.
• Perform FPGA synthesis and timing closure.
• Verify hardware and troubleshoot with lab gear.
• Support RF and software engineering teams.

Skills

FPGA design

Fixed-point DSP

Clock-domain design

Xilinx FPGAs & Vivado

Education

Bachelor of Science in Electrical Engineering

Tools

Xilinx Vivado

MATLAB

Job description

Motorola Solutions, via its Silvus Technologies subsidiary, seeks a Senior FPGA Design Engineer focused on signal processing in a West Los Angeles setting. Hybrid role requiring at least three onsite days per week.

The engineer will drive RTL development, DSP, and fixed-point implementations for high-performance wireless projects. Ideal candidates have 6+ years FPGA experience (or 4 with a Master, 2 with a PhD), Xilinx/Vivado expertise, and the ability to work across clock domains with strong