Principal FPGA & RTL Design Engineer – Signal Processing

Silvus; Irvine (CA); On-site; USD 165,000 - 250,000; Full time

Job summary

Silvus is looking for a Principal FPGA / RTL Design Engineer - Signal Processing in Irvine, California. The role involves collaboration with the FPGA Engineering team to participate in the entire R&D process from concept to deployment. The successful candidate will have over 10 years of experience in RTL design and FPGA implementations.

This position offers a salary range of $165,000 to $250,000 based on experience and qualifications.

Qualifications

• Minimum 10 years of experience in RTL design and FPGA implementation.
• Deep knowledge of fixed-point binary arithmetic and DSP designs.
• Experience with front-end RTL design tools.

Responsibilities

• Work with system engineers on wireless communication projects.
• Perform RTL coding, simulation, and test bench development.
• Conduct hardware verification and troubleshooting.

Skills

RTL design fundamentals using Verilog

FPGA synthesis and timing closure

Digital signal processing (DSP)

Scripting languages (Perl, Python)

Education

Bachelor of Science degree in Electrical Engineering or related fields

MS or Ph.D. in relevant fields (preferred)

Tools

Xilinx FPGAs and the Vivado IDE

Job description

Silvus is looking for a Principal FPGA / RTL Design Engineer - Signal Processing in Irvine, California. The role involves collaboration with the FPGA Engineering team to participate in the entire R&D process from concept to deployment. The successful candidate will have over 10 years of experience in RTL design and FPGA implementations.

This position offers a salary range of $165,000 to $250,000 based on experience and qualifications.