Senior Space Design Verification Engineer

Viasat; Tempe (AZ); On-site; USD 133,000 - 197,000; Full time

Job summary

Viasat is seeking a Senior Design Verification Engineer in the United States to lead RTL verification for FPGA and ASIC designs. You will create tests, develop SystemVerilog/UVM testbenches, and drive coverage and regressions with the RTL team.

You will evaluate tools like Questa, Xcelium and VCS, manage resources, and ensure timely delivery in a fast-paced, site-based environment. Travel up to 10% may be required.

Qualifications

• Bachelor's degree in electrical or computer engineering or related field.
• 5+ years of design verification experience including UVM testbench experience.
• Experience with digital logic and timing considerations.
• Proven ability to follow coding guidelines and participate in code reviews.
• Experience with Questa, Xcelium and VCS simulators.

Responsibilities

• Create drivers, monitors, scoreboards, sequences and model predictors for interfaces and designs.
• Maintain program schedule and task tracking using Agile Jira.
• Debug failing tests and collaborate with RTL developers.
• Run and analyze regressions.

Skills

SystemVerilog

UVM

Testbench development

Debugging

Coverage analysis

Agile Jira

RTL verification

Tool evaluation

License management

Education

Bachelor's Degree in Electrical Engineering

or Computer Engineering

Tools

Questa

Xcelium

VCS

Job description

Viasat is seeking a Senior Design Verification Engineer in the United States to lead RTL verification for FPGA and ASIC designs. You will create tests, develop SystemVerilog/UVM testbenches, and drive coverage and regressions with the RTL team.

You will evaluate tools like Questa, Xcelium and VCS, manage resources, and ensure timely delivery in a fast-paced, site-based environment. Travel up to 10% may be required.