Senior FPGA Engineer – RTL to Production, Timing Closure

Actalent; Tallahassee (FL); Hybrid; USD 114,000 - 139,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance (AD&D)

HSA & Wellness perks

PTO / Vacation / Sick Leave

Job summary

Actalent in Newtown, PA, is seeking an experienced FPGA Engineer to design and develop RTL-focused FPGA products, collaborating with hardware and software teams for robust deployments.

The role emphasizes timing closure, FPGA simulation and verification, and hands-on lab debugging, with 7–10 years of RTL/FPGA experience and familiarity with Xilinx and other FPGA families. This contract-to-hire position offers a hybrid workplace in Newtown, PA.

Qualifications

• 7–10 years of experience in RTL design and FPGA development.
• Hands-on RTL coding experience, preferably VHDL; Verilog also acceptable.
• Experience achieving timing closure on high-speed FPGA designs through timing analysis and optimization.
• Experience FPGA simulation and verification prior to hardware deployment.
• Familiarity with Xilinx FPGAs; Microchip and Intel/Altera also valuable.

Responsibilities

• Design and develop FPGA-based products with a focus on RTL design, FPGA development, and simulation.
• Collaborate with hardware, embedded software, and test engineers to ensure seamless product development.
• Perform simulation and verification to validate designs before hardware deployment.
• Achieve timing closure on high-speed FPGA designs through timing analysis and optimization.
• Provide product development support and engage in lab debugging and troubleshooting.

Skills

FPGA design

RTL coding

Timing analysis

FPGA verification

Xilinx experience

Python scripting

TCL scripting

Lab debugging

Tools

Xilinx FPGA

Microchip

Intel/Altera

Job description

Actalent in Newtown, PA, is seeking an experienced FPGA Engineer to design and develop RTL-focused FPGA products, collaborating with hardware and software teams for robust deployments.

The role emphasizes timing closure, FPGA simulation and verification, and hands-on lab debugging, with 7–10 years of RTL/FPGA experience and familiarity with Xilinx and other FPGA families. This contract-to-hire position offers a hybrid workplace in Newtown, PA.