Senior FPGA Engineer — RTL & Timing Closure Expert

Actalent; United States; Hybrid; USD 76,000 - 92,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Hybrid work model

Job summary

Actalent is seeking an experienced FPGA Engineer to design and develop FPGA-based products with strong RTL focus. You will collaborate with hardware, embedded software, and test teams to ensure robust designs are validated through simulation and verification before deployment.

The role emphasizes achieving timing closure on high-speed FPGA designs, utilizing Xilinx toolchains, and hands-on debugging in the lab. 7–10 years of experience is preferred and the position is hybrid in Newtown, PA.

Qualifications

• 7–10 years of experience in RTL design, FPGA development, simulation and verification.
• Experience achieving timing closure on high-speed FPGA designs.
• Familiarity with FPGA toolchains and lab debugging.

Responsibilities

• Design and develop FPGA-based products with RTL and simulation focus.
• Collaborate with hardware, embedded software, and test engineers.
• Perform simulation and verification before hardware deployment.
• Achieve timing closure on high-speed FPGA designs through timing analysis.
• Provide product development support and lab debugging.

Skills

RTL coding

Timing closure

FPGA design

Simulation & verification

Tools

Xilinx FPGA

Microchip

Intel/Altera

Job description

Actalent is seeking an experienced FPGA Engineer to design and develop FPGA-based products with strong RTL focus. You will collaborate with hardware, embedded software, and test teams to ensure robust designs are validated through simulation and verification before deployment.

The role emphasizes achieving timing closure on high-speed FPGA designs, utilizing Xilinx toolchains, and hands-on debugging in the lab. 7–10 years of experience is preferred and the position is hybrid in Newtown, PA.