Senior FPGA Engineer: RTL, Verification & Debug Lead

Celestica Inc.; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Celestica Inc. in Richardson, TX is seeking a Senior Staff FPGA Engineer to drive RTL design, verification, and back‑end flow for advanced hardware platform solutions.

You will collaborate with platform architects, board designers, and software teams to ensure robust delivery and timely debugging on real hardware. Required: 12+ years in FPGA design; strong Verilog/SystemVerilog; experience with Xilinx/Intel FPGAs, PCIe, DDR, LVDS; familiarity with UVM and ModelSim/Vivado/Quartus; excellent

Qualifications

• 12+ years of FPGA design experience in complex hardware projects.
• Deep knowledge of Verilog and SystemVerilog; RTL design and simulation.
• Experience with Xilinx and Intel (Altera) FPGAs; PCIe, DDR, LVDS knowledge.
• Familiarity with UVM and coverage-driven verification techniques.

Responsibilities

• Drive RTL design, verification, and back-end flow for FPGA projects.
• Collaborate with platform architects, board designers, and software teams.
• Ensure on-time delivery, debugging on real hardware, and schedule estimates.
• Mentor junior design engineers and communicate project status.

Skills

FPGA design

Verilog/SystemVerilog

UVM/verification

RTL debugging

Cross-functional

Communication

Education

Bachelor/Master in EE/CS/CE

Tools

Vivado

Quartus II

ModelSim

ISE

Timing analysis

Job description

Celestica Inc. in Richardson, TX is seeking a Senior Staff FPGA Engineer to drive RTL design, verification, and back‑end flow for advanced hardware platform solutions.

You will collaborate with platform architects, board designers, and software teams to ensure robust delivery and timely debugging on real hardware. Required: 12+ years in FPGA design; strong Verilog/SystemVerilog; experience with Xilinx/Intel FPGAs, PCIe, DDR, LVDS; familiarity with UVM and ModelSim/Vivado/Quartus; excellent