Senior FPGA Engineer — Onsite Boston, Impact & Equity

Ayosemi; Boston (MA); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Equity

Job summary

Ayo sem i in Boston is seeking a Senior FPGA Engineer to join our hardware team. You will write and deploy RTL and embedded C/C++ code on FPGAs central to our chip development and verification workflow.

This hands-on role requires real hardware experience, collaboration with AI and hardware teams, and ownership of prototype builds from bring-up to test benches as we scale our FPGA infrastructure.

Qualifications

• RTL proficiency in Verilog or VHDL mandatory.
• Real industry FPGA experience with deployed code on real hardware.
• Strong programming ability beyond RTL.
• Familiarity with FPGA platforms (Xilinx/AMD preferred; others OK).
• Embedded systems experience with ADC/DAC interfaces is a plus.

Responsibilities

• Design, implement, and test FPGA-based systems for chip verification and prototype development.
• Deploy and iterate RTL code (Verilog or VHDL) targeting FPGAs in prototype hardware.
• Deploy and iterate embedded C/C++ code targeting embedded processors on FPGA SoCs.
• Support FPGA trade studies and pin-mapping viability for developmental PCBs.
• Assist bring-up and test of PCBs and prototypes by writing/testing interfaces to peripherals.
• Collaborate with ASIC engineers to build test benches and validate chips.
• Upgrade and scale existing FPGA infrastructure as we grow.

Skills

RTL proficiency

Verilog

VHDL

C/C++

FPGA platforms

Embedded systems

ASIC verification workflows

Education

Bachelor's or Master's degree in Electrical Engineering or related

Job description

Ayo sem i in Boston is seeking a Senior FPGA Engineer to join our hardware team. You will write and deploy RTL and embedded C/C++ code on FPGAs central to our chip development and verification workflow.

This hands-on role requires real hardware experience, collaboration with AI and hardware teams, and ownership of prototype builds from bring-up to test benches as we scale our FPGA infrastructure.