Senior FPGA Design Engineer — Verilog & Versal ACAP

GCS Recruitment; Vancouver (WA); On-site; USD 120,000 - 180,000; Full time

Job summary

GCS Recruitment is seeking an experienced FPGA Design Engineer to design and develop advanced FPGA solutions for a satellite communications system. You will collaborate with system architects and cross-functional teams to define, implement, validate and release FPGA-based solutions for high-performance networking applications.

You will own FPGA bitstreams, perform RTL design and verification, and lead physical implementation including timing closure.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 7+ years of hands-on FPGA design experience.
• Strong expertise with Verilog HDL for RTL design and verification.
• Experience designing with AMD Xilinx Versal ACAP FPGA architecture.
• Experience working with Microchip IGLOO2 FPGA platforms.

Responsibilities

• Own the development and delivery of one or more FPGA bitstreams.
• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA development across the complete lifecycle: microarchitecture, RTL design, physical implementation, timing closure, simulation & verification, lab validation, production release.
• Develop FPGA-based networking and digital communication functions.
• Collaborate with system architects, hardware engineers, firmware, and software teams.
• Build FPGA prototypes to evaluate architecture and design tradeoffs.
• Support hardware bring-up, system integration, and debugging involving FPGA, RF, firmware, and networking components.
• Perform synthesis, place & route, timing analysis, and design optimization.
• Develop testbenches and simulation environments; debug in simulation and hardware.
• Drive design tradeoff analysis focused on performance, power, cost, area, and customer experience.
• Create technical documentation including design specs, verification plans, and test documentation.
• Support manufacturing, production deployment, and post-release engineering activities.

Skills

Verilog HDL

SystemVerilog

RTL Design

FPGA Verification

Timing Closure

CDC Analysis

Physical Implementation

Hardware Bring-up

Python

TCL

Perl

Git

SVN

Clock Domain Crossing

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Vivado

Libero SoC

ModelSim

Vivado Simulator

VCS

Git

SVN

Job description

GCS Recruitment is seeking an experienced FPGA Design Engineer to design and develop advanced FPGA solutions for a satellite communications system. You will collaborate with system architects and cross-functional teams to define, implement, validate and release FPGA-based solutions for high-performance networking applications.

You will own FPGA bitstreams, perform RTL design and verification, and lead physical implementation including timing closure.