Senior FPGA Engineer for AI Compute Architectures

Everest Consultants, Inc.; Oregon; On-site; USD 170,000 - 210,000; Full time

Job summary

Everest Consultants, Inc. seeks a Senior FPGA Engineer to design, implement, and optimize FPGA-based solutions for AI workloads, focusing on RTL and HLS design and system-level verification on high-performance FPGA platforms.

You will collaborate with architecture, software and validation teams to meet performance, power and reliability targets, contribute to design reviews, and help define best practices for FPGA development within the organization.

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience.
• 8+ years FPGA or digital-design experience with complex production or advanced-development systems.
• Strong RTL design proficiency for FPGA/ASIC with Verilog-based work.
• Hands-on experience with PCIe-connected FPGA platforms, DMA, AXI4/AXI4-Lite/AXI4-Stream.
• Knowledge of HBM/DDR memory architectures and timing closure.
• Experience in FPGA hardware verification and debugging with simulations, assertions, and regression.
• Experience with Vivado/Vitis HLS, Linux, Python, Tcl, Git, and C/C++ host software.

Responsibilities

• Design, implement, and optimize FPGA modules for AI computing architectures.
• RTL and HLS design and system-level verification on high-performance FPGA platforms.
• Debug hardware issues and collaborate with architecture, software, and validation teams.
• Contribute to design reviews, maintain documentation, and define best practices for FPGA development.

Skills

FPGA/digital-design experience

RTL design proficiency

C/C++ HLS

Cross-functional collaboration

Documentation & test results

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Verilog

Vitis HLS

Vivado

Linux

Python

Tcl

Git

C/C++

Job description

Everest Consultants, Inc. seeks a Senior FPGA Engineer to design, implement, and optimize FPGA-based solutions for AI workloads, focusing on RTL and HLS design and system-level verification on high-performance FPGA platforms.

You will collaborate with architecture, software and validation teams to meet performance, power and reliability targets, contribute to design reviews, and help define best practices for FPGA development within the organization.