Senior FPGA Engineer

GCS Recruitment; United States; On-site; USD 90,000 - 130,000; Full time

Job summary

GCS Recruitment is seeking an FPGA Engineer to design and integrate programmable logic for phased-array satellite systems. You will contribute to the digital signal chain, interface with custom silicon, beamforming devices, modems, and network processors, and lead lab-based validation efforts.

The role blends FPGA design with hands-on hardware integration and validation in a fast-paced environment, requiring strong debugging skills using JTAG and on-chip analysis tools.

Qualifications

• Experience designing FPGA-based digital signal chains.
• Strong RTL coding and verification skills.
• Experience with high-speed data interfaces and validation.

Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array systems.
• Create RTL for data movement, control, monitoring, and integration of DSP chains.
• Implement high-speed FPGA interfaces including multi-gigabit SerDes and JESD links.
• Perform timing closure, constraints development, optimization, and build management.

Skills

FPGA design

RTL coding

Timing closure

High-speed interfaces

SerDes

JESD links

JTAG debugging

Lab equipment

Documentation

Job description

About the Project

Join an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.

The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands‑on hardware integration and validation in a fast‑paced engineering environment.

Key Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array communication systems.
• Create RTL for data movement, control, monitoring, and integration functions within the digital signal chain.
• Implement and validate high-speed FPGA interfaces, including multi-gigabit SerDes and JESD-class communication links.
• Perform timing closure, constraints development, optimization, and build management to ensure reliable hardware performance.
• Support FPGA bring-up, debugging, and validation on newly developed hardware platforms.
• Work alongside hardware engineers to troubleshoot system-level issues using JTAG, on‑chip logic analyzers, and laboratory test equipment.
• Develop diagnostic and monitoring capabilities, including error detection, status reporting, and debug infrastructure.
• Participate in system integration, testing, and validation activities.
• Collaborate with multidisciplinary engineering teams to deliver project milestones.
• Produce and maintain design documentation and technical deliverables.

What You'll Be Working On

You will develop FPGA functionality that supports data flow across advanced phased-array electronics, enabling communication between processing devices, modems, beamforming hardware, and antenna systems. The role requires a combination of strong FPGA design expertise and hands‑on lab experience to ensure high-speed interfaces perform reliably in real hardware environments.

GCS is acting as an Employment Business in relation to this vacancy.