Senior FPGA Engineer

GCS Recruitment; Orlando (FL); On-site; USD 90,000 - 140,000; Full time

Job summary

GCS Recruitment is seeking an FPGA Engineer to design and integrate programmable logic for phased-array communication systems. The role involves RTL development, timing closure, and close collaboration with hardware engineers to ensure reliable data paths across FPGA hardware and custom silicon.

You will use JTAG and logic analyzers in a fast-paced lab, contributing to system integration, testing, and verification across multiple hardware platforms.

Qualifications

• Experience designing FPGA-based digital signal chains for high-speed data paths.
• Hands-on hardware integration and validation in lab environments.
• Proficient with timing closure, constraints, and build management.

Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array systems.
• Create RTL for data movement, control, monitoring within the DSP chain.
• Implement high-speed FPGA interfaces and JESD-class links.
• Perform timing closure and build management for reliable hardware.
• Support FPGA bring-up, debugging, and validation on new hardware.

Skills

FPGA design

RTL development

Timing closure

System integration

Diagnostics

Tools

JTAG

Logic analyzers

Lab equipment

SerDes

On‑chip debugging

Job description

About the Project

Join an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.

The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands‑on hardware integration and validation in a fast‑paced engineering environment.

Key Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array communication systems.
• Create RTL for data movement, control, monitoring, and integration functions within the digital signal chain.
• Implement and validate high-speed FPGA interfaces, including multi-gigabit SerDes and JESD-class communication links.
• Perform timing closure, constraints development, optimization, and build management to ensure reliable hardware performance.
• Support FPGA bring-up, debugging, and validation on newly developed hardware platforms.
• Work alongside hardware engineers to troubleshoot system-level issues using JTAG, on‑chip logic analyzers, and laboratory test equipment.
• Develop diagnostic and monitoring capabilities, including error detection, status reporting, and debug infrastructure.
• Participate in system integration, testing, and validation activities.
• Collaborate with multidisciplinary engineering teams to deliver project milestones.
• Produce and maintain design documentation and technical deliverables.

What You'll Be Working On

You will develop FPGA functionality that supports data flow across advanced phased-array electronics, enabling communication between processing devices, modems, beamforming hardware, and antenna systems. The role requires a combination of strong FPGA design expertise and hands‑on lab experience to ensure high-speed interfaces perform reliably in real hardware environments.

GCS is acting as an Employment Business in relation to this vacancy.