Senior FPGA Engineer

GCS Recruitment; Coronado (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

GCS Recruitment is partnering with a space-tech client to hire a Senior FPGA Engineer for a growing LEO satellite constellation.

You will design and verify RTL on AMD/Xilinx Versal and UltraScale+ devices, bring up high-speed transceivers, and develop embedded Linux environments with PetaLinux/Yocto. This on-site role in Coronado, CA offers exposure to cutting-edge aerospace hardware and collaboration with hardware engineering teams.

Qualifications

• 8+ years of FPGA RTL development using Verilog/SystemVerilog or VHDL.
• Hands-on with GTY/GTM transceivers and 25G/50G/100G Ethernet.
• Board bring-up and hardware debugging experience.
• Timing closure on modern FPGA devices.
• U.S. Citizenship or Permanent Residency required.

Responsibilities

• Design, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.
• Configure and bring up GTY-class transceivers and debug 25 Gbps+ links.
• Implement high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).
• Develop embedded Linux environments with PetaLinux/Yocto.
• Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.
• Collaborate with hardware engineers to support system validation and debugging.
• Create diagnostic and monitoring tools to support development and test activities.

Skills

FPGA RTL development

Verilog/SystemVerilog/VHDL

High-speed transceivers

Hardware debugging

Embedded Linux

Tools

PetaLinux

Yocto

JTAG

ILA

Job description

Senior FPGA Engineer

About the Opportunity

Our client is building one of the world's largest low-Earth-orbit (LEO) satellite constellations, delivering broadband internet from space. With hundreds of satellites already in orbit and thousands more planned, they are developing the next generation of space-based communications technology.

The hardware team designs the advanced electronics powering phased-array antennas, including complex multi-layer boards, custom silicon, and high-speed serial interfaces. Engineers on this team have the unique opportunity to see their designs deployed on satellites operating in orbit.

What You’ll Do

• Design, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.
• Configure and bring up GTY-class transceivers and debug 25 Gbps+ serial links.
• Implement and validate high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).
• Develop and maintain embedded Linux environments using PetaLinux/Yocto.
• Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.
• Work closely with hardware engineers to support system validation and debugging.
• Create diagnostic and monitoring tools to support development and test activities.

Required Qualifications

• 8+ years of FPGA/RTL development experience using Verilog, SystemVerilog, or VHDL.
• Hands-on experience with high-speed serial transceivers (GTY/GTM) and/or 25G/50G/100G Ethernet.
• Proven board bring-up and hardware debugging experience.
• Experience achieving timing closure on modern FPGA devices.
• U.S. Citizenship or Permanent Residency required.

Preferred Qualifications

• Experience with AMD/Xilinx Versal ACAP and UltraScale+ platforms.
• MRMAC or CMAC configuration and optimization experience.
• Strong background in PetaLinux, Yocto, device trees, and embedded Linux drivers.

Nice to Have

• Experience with JESD204, Aurora, or similar high-speed protocols.
• Aerospace, satellite communications, radar, or networking experience.
• Familiarity with high-reliability or radiation-aware designs.
• FPGA prototyping experience supporting ASIC development.

Why Join?
Work on cutting-edge satellite technology, collaborate with top-tier engineering teams, and see your FPGA designs deployed on real hardware headed for orbit.