Senior FPGA Engineer: Phased-Array Satellite Systems

GCS Recruitment; Redmond (WA); Sur place; USD 120 000 - 170 000; Plein temps

Résumé du poste

GCS Recruitment is seeking an experienced FPGA Engineer to design and integrate FPGA-based solutions for a next-generation phased-array payload electronics program in a satellite context. You will bridge processing devices, modems, beamforming hardware, and antenna systems, with emphasis on high-speed interfaces and robust hardware validation.

The role combines hands-on lab work with RTL development, timing closure, and system integration, requiring familiarity with JTAG, test equipment, and

Qualifications

• Experience designing FPGA-based digital signal chain components.
• Proficient RTL development for complex data paths and control logic.
• Experience with high-speed interfaces and JESD-class links.

Responsabilités

• Design, develop, and integrate FPGA-based solutions for phased-array comms.
• Create RTL for data movement, control, monitoring, and integration.
• Implement and validate high-speed FPGA interfaces (multi-gigabit SerDes).
• Perform timing closure, constraints development, optimization, and build management.
• Support FPGA bring-up, debugging, and validation on new hardware.
• Troubleshoot system-level issues with JTAG and lab equipment.
• Develop diagnostic and monitoring capabilities, including error detection.
• Collaborate with multidisciplinary teams to meet milestones.
• Produce and maintain design documentation and technical deliverables.

Connaissances

FPGA design

RTL development

SerDes interfaces

Timing closure

Hardware validation

JTAG debugging

System integration

Outils

Lab equipment

JTAG tools

Description du poste

About the Project

Join an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.

The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands-on hardware integration and validation in a fast-paced engineering environment.

Key Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array communication systems.
• Create RTL for data movement, control, monitoring, and integration functions within the digital signal chain.
• Implement and validate high-speed FPGA interfaces, including multi-gigabit SerDes and JESD-class communication links.
• Perform timing closure, constraints development, optimization, and build management to ensure reliable hardware performance.
• Support FPGA bring-up, debugging, and validation on newly developed hardware platforms.
• Work alongside hardware engineers to troubleshoot system-level issues using JTAG, on-chip logic analyzers, and laboratory test equipment.
• Develop diagnostic and monitoring capabilities, including error detection, status reporting, and debug infrastructure.
• Participate in system integration, testing, and validation activities.
• Collaborate with multidisciplinary engineering teams to deliver project milestones.
• Produce and maintain design documentation and technical deliverables.

What You'll Be Working On

You will develop FPGA functionality that supports data flow across advanced phased-array electronics, enabling communication between processing devices, modems, beamforming hardware, and antenna systems. The role requires a combination of strong FPGA design expertise and hands-on lab experience to ensure high-speed interfaces perform reliably in real hardware environments.

GCS is acting as an Employment Business in relation to this vacancy.