Senior FPGA Engineer - Phased-Array & High-Speed Links

GCS Recruitment; United States; On-site; USD 90,000 - 130,000; Full time

Job summary

GCS Recruitment is seeking an FPGA Engineer to design and integrate programmable logic for phased-array satellite systems. You will contribute to the digital signal chain, interface with custom silicon, beamforming devices, modems, and network processors, and lead lab-based validation efforts.

The role blends FPGA design with hands-on hardware integration and validation in a fast-paced environment, requiring strong debugging skills using JTAG and on-chip analysis tools.

Qualifications

• Experience designing FPGA-based digital signal chains.
• Strong RTL coding and verification skills.
• Experience with high-speed data interfaces and validation.

Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array systems.
• Create RTL for data movement, control, monitoring, and integration of DSP chains.
• Implement high-speed FPGA interfaces including multi-gigabit SerDes and JESD links.
• Perform timing closure, constraints development, optimization, and build management.

Skills

FPGA design

RTL coding

Timing closure

High-speed interfaces

SerDes

JESD links

JTAG debugging

Lab equipment

Documentation

Job description

GCS Recruitment is seeking an FPGA Engineer to design and integrate programmable logic for phased-array satellite systems. You will contribute to the digital signal chain, interface with custom silicon, beamforming devices, modems, and network processors, and lead lab-based validation efforts.

The role blends FPGA design with hands-on hardware integration and validation in a fast-paced environment, requiring strong debugging skills using JTAG and on-chip analysis tools.