CPU Emulation Engineer, Silicon

Google; Town of Montana (WI); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking an experienced CPU Emulation Engineer, Silicon to push the boundaries of custom silicon solutions powering Google’s hardware products. You will help craft RTL partitions and FPGA-based validation, driving pre-silicon verification and performance benchmarking across enterprise emulation platforms.

Qualified candidates have a strong background in RTL design, emulation platforms, and automation scripting, with a track record of mentoring and delivering scalable hardware solutions

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8 years of experience with emulation or FPGA prototyping platforms.
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect and drive RTL partitioning, FPGA synthesis, and validation strategies for emulation platforms.
• Define and execute test suites, performance benchmarks, and software workloads for pre-silicon verification and system-level validation.
• Guide advanced debugging methodologies to isolate and resolve complex functional failures in multi-million gate subsystem designs.
• Lead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across emulation farms.
• Architect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline CI.

Skills

RTL design with Verilog/SystemVerilog

Automation scripting

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Synopsys ZeBu/HAPS

Cadence Palladium/Protium

Siemens Veloce

Job description

CPU Emulation Engineer, Silicon

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, Siemens Veloce).
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Preferred Qualifications

• Experience scaling compilation and routing across multi-FPGA and enterprise emulation platforms.
• Experience verifying and troubleshooting complex semiconductor IP blocks.
• Experience collaborating with cross-functional design verification (DV) and silicon design teams.

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

Salary

• US Salary: $163,000 - $236,000 (USD) + 15% bonus target + equity + benefits
• Learn more about benefits at Google.

Responsibilities

• Architect and drive advanced Register-Transfer Level (RTL) partitioning, Field-Programmable Gate Array (FPGA) synthesis, and validation strategies for industry-standard emulation platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce.
• Define and execute comprehensive test suites, complex performance benchmarks, and software workloads to ensure pre-silicon verification and system-level validation.
• Guide advanced debugging methodologies to rapidly isolate and resolve complex functional failures within multi-million gate subsystem designs and full-chip environments.
• Lead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across enterprise emulation farms.
• Architect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline continuous integration.

Locations

• Austin, TX, USA
• Mountain View, CA, USA
• +3 more
• +2 more

Preferred Locations

• Austin, TX, USA
• Mountain View, CA, USA
• Portland, OR, USA
• Poughkeepsie, NY, USA

Additional Information

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We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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