Senior Design Verification Engineer (remote)

Chelsea Search Group, Inc.; Portland (OR); Remote; USD 90,000 - 150,000; Full time

Job summary

An innovative firm is seeking a Senior Design Verification Engineer to join their dynamic team. In this fully remote role, you will leverage your expertise in SoC verification, utilizing SystemVerilog and UVM to develop and execute comprehensive verification plans. You will be instrumental in creating and maintaining testbenches, running simulations, and documenting results to ensure high-quality digital designs. This position offers a unique opportunity to contribute to cutting-edge methodologies and work collaboratively across teams. If you thrive in a fast-paced environment and are passionate about advancing technology, this role is perfect for you.

Benefits

Benefits

401k

Stock Options

Qualifications

• 5+ years of experience in SoC verification with UVM and SystemVerilog.
• Strong background in digital design and ASIC development flow.

Responsibilities

• Develop and execute verification plans for digital designs using SystemVerilog.
• Document verification strategies and results comprehensively.

Skills

SoC verification using UVM

SystemVerilog

Digital design concepts

C/C++/Python/Perl programming

Gate level simulation setup

Communication skills

Multi-tasking and prioritization

Education

BSEE/MSEE

Tools

Synopsys VCS

Verdi

Spyglass

Git

Job description

Senior Design Verification Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Responsibilities:

1. Develop and execute verification plans for digital designs using SystemVerilog and UVM
2. Create and maintain testbenches, test cases, and test vectors
3. Contribute to the development of novel methodologies and verification techniques
4. Run simulations to verify design against specifications and analyze results, identify issues, and debug designs
5. Implement coverage tracking and metrics
6. Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies
7. Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.

Required Skills:

1. BSEE/MSEE with 5+ years of hands-on experience in SoC verification using UVM
2. Experience in gate level simulation setup and process corner failure analysis
3. Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass
4. Experience with digital design concepts and ASIC development flow
5. Experience writing and debugging RTL using SystemVerilog
6. Programming experience using C, C++, and/or Python/Perl
7. Ability to work collaboratively across teams and communicate effectively
8. Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects

Preferred Skills:

1. Experience verifying high-speed interfaces such as PCIe and DDR
2. Experience verifying RISC-V based systems
3. Experience with emulation or FPGA prototyping
4. Experience with formal verification methodologies
5. Experience with the Chisel hardware description language
6. Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines

#SoC #UVM #SystemVerilog #SoCDesign #DesignVerification