Senior FPGA Design Engineer — RFSoC/Versal (Hybrid)

Fairwinds Technologies, LLC; Herndon (VA); Hybrid; USD 120.000 - 170.000; Vollzeit

Zusammenfassung

Fairwinds Technologies is seeking an FPGA Design Engineer to develop RTL in Verilog/VHDL for Zynq UltraScale+ RFSoC/Versal platforms. You will collaborate with DSP and embedded teams to deliver wideband RF signal processing on PCB-based hardware.

You will perform timing closure, validation, and debug with JTAG/ILA tools, and contribute to prototype-to-production transitions in a DoD-relevant environment.

Qualifikationen

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• 10+ years FPGA design and development experience.
• Strong proficiency in Verilog and/or VHDL.
• Deep experience with RTL simulation tools such as Siemens Questa and Vivado Simulator.
• Hands-on experience using Xilinx Vivado for synthesis, implementation, timing closure, and debug.
• Experience with Xilinx Zynq UltraScale+ RFSoC and Versal devices.
• Experience developing FPGA designs for PCB-based embedded systems.
• Experience implementing complex DSP designs and translating algorithm specifications into RTL.
• Strong understanding of AXI protocols, clock domain crossing, resets, and timing constraints.
• Experience with FPGA debugging tools such as ILA, VIO, and JTAG-based debugging.
• U.S. Citizenship and an active DoD Secret (or higher) security clearance (or ability to obtain).
• Experience integrating FPGA designs with high-speed data converters (ADRV9009, AD9081) or TI AFE/ADC products.
• Experiment with multi-sample per clock architectures for high-throughput signal processing.
• Fundamental RF signal processing concepts including sampling theory, digital mixing, filtering, and frequency conversion.

Aufgaben

• Design, implement, and verify FPGA logic using Verilog and VHDL within the Xilinx Vivado toolchain for Zynq UltraScale+ RFSoC, MPSoC and Versal devices.
• Develop programmable logic architectures for signal processing, control, and high-speed data movement applications.
• Implement complex DSP algorithms into efficient FPGA fabric designs (filters, FFTs, channelizers, modulators, demodulators, decimation/interpolation, fixed-point optimization).
• Work with embedded software engineers to define and implement PL–PS interfaces, including AXI-Lite, AXI-Stream, DMA, interrupts, and register maps.
• Integrate FPGA designs with embedded processors and heterogeneous compute architectures (e.g., Zynq UltraScale+ MPSoC, RFSoC, Versal ACAP).
• Perform functional simulation, static timing analysis, and resource optimization to meet performance, latency, and power constraints.
• Support FPGA bring-up and debugging on custom PCB hardware using lab tools such as JTAG, Integrated Logic Analyzer (ILA), logic analyzers, and oscilloscopes.
• Participate in system integration and debug efforts spanning FPGA logic, embedded software, DSP algorithms, and hardware.
• Develop test benches, validation strategies, and design documentation, including FPGA design descriptions, interface control documents (ICDs), and SBIR deliverables as required.
• Support prototype-to-production transitions, including ECOs, version control, and configuration management.
• Design and integrate interfaces with high-speed data converters from Analog Devices (e.g., ADRV9009, AD9081) and Texas Instruments, including JESD204B/C and LVDS interfaces.
• Develop multi-sample per clock (parallel sample) architectures to meet throughput requirements for wideband RF signal processing applications.
• Apply fundamental RF signal processing knowledge to support digital front-end design including NCOs, mixers, digital up/down conversion, and gain control.

Kenntnisse

Verilog

VHDL

RTL design

AXI protocols

DSP algorithms

FPGA debugging

I/O interfaces

Ausbildung

Bachelor’s degree in Electrical/Computer Engineering or related field

Tools

Xilinx Vivado

Questa

Vivado Simulator

ILA/VIO

JESD204B/C

ADRV9009/AD9081

Jobbeschreibung

Fairwinds Technologies is seeking an FPGA Design Engineer to develop RTL in Verilog/VHDL for Zynq UltraScale+ RFSoC/Versal platforms. You will collaborate with DSP and embedded teams to deliver wideband RF signal processing on PCB-based hardware.

You will perform timing closure, validation, and debug with JTAG/ILA tools, and contribute to prototype-to-production transitions in a DoD-relevant environment.