Senior FPGA/ASIC Logic Design Engineer (Quantum/Low-Latency)

DCV Technologies; United States; À distance; USD 120 000 - 180 000; Plein temps

Résumé du poste

DCV Technologies seeks an Expert Logic Design Engineer (FPGA/ASIC) for an advanced R&D project developing FPGA- and ASIC-based control and measurement systems used in quantum computing.

You will take technical ownership of complex, high-performance digital subsystems, focusing on deterministic timing, low latency, and design quality in a collaborative environment with verification, software and hardware teams.

Qualifications

• 6+ years native FPGA/ASIC digital logic design experience.
• Expert hands-on SystemVerilog RTL design.
• Ownership of complex digital IP from spec to implementation.

Responsabilités

• Lead digital architecture, microarchitecture and SystemVerilog RTL implementation.
• Design configurable, ultra-low-latency digital logic and reusable IP.
• Drive design from specification through synthesis, timing closure and integration.
• Optimize clocking, CDC, resource utilization, power and critical paths.
• Collaborate with verification, software and hardware engineering teams.
• Guide technical decisions, design reviews and engineering improvements.

Connaissances

SystemVerilog RTL

FPGA/ASIC design

Digital architecture

Timing closure

Technical leadership

English (B2+)

Outils

Vivado

Questa/VCS

Python

Tcl

AXI/PCIe/DDR

DSP

Description du poste

DCV Technologies seeks an Expert Logic Design Engineer (FPGA/ASIC) for an advanced R&D project developing FPGA- and ASIC-based control and measurement systems used in quantum computing.

You will take technical ownership of complex, high-performance digital subsystems, focusing on deterministic timing, low latency, and design quality in a collaborative environment with verification, software and hardware teams.