Senior FPGA/ASIC Logic Designer for Real-Time Control

DCV Technologies

United States

Remote

USD 120,000 - 180,000

Full time

7 days ago
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Job summary

DCV Technologies is seeking a Senior Logic Design Engineer to develop high-performance FPGA/ASIC digital logic for advanced quantum computing control and measurement technology. This hands-on role designs configurable, low-latency hardware and collaborates with architects, verification engineers and software specialists.

The position requires 4+ years of FPGA/ASIC design experience, strong SystemVerilog RTL skills and a solid understanding of digital microarchitecture.

Qualifications

  • 4+ years of professional FPGA/ASIC digital logic design experience.
  • Strong hands-on SystemVerilog RTL development.
  • Solid understanding of digital microarchitecture and synchronous design.
  • Experience with synthesis, STA, timing optimization and CDC.
  • Practical FPGA/ASIC implementation and RTL debugging experience.
  • Confident English (B2+).

Responsibilities

  • Design and implement complex SystemVerilog RTL modules.
  • Develop signal processing, waveform generation and real-time control logic.
  • Contribute to architecture, microarchitecture and RTL integration.
  • Perform synthesis, static timing analysis and optimization.
  • Debug and verify RTL functionality with verification teams.
  • Integrate digital IP and hardware-software interfaces.

Skills

SystemVerilog RTL
FPGA/ASIC
Digital logic design
Synthesis/STA
RTL debugging
English B2+

Tools

Vivado
Questa/VCS
Python/Tcl

Job description

DCV Technologies is seeking a Senior Logic Design Engineer to develop high-performance FPGA/ASIC digital logic for advanced quantum computing control and measurement technology. This hands-on role designs configurable, low-latency hardware and collaborates with architects, verification engineers and software specialists.

The position requires 4+ years of FPGA/ASIC design experience, strong SystemVerilog RTL skills and a solid understanding of digital microarchitecture.

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