Senior FPGA/ASIC Design Engineer (Active Secret Clearance)

Entegee; Camden (NJ); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401K plan

Paid time off

Job summary

Entegee seeks a mid-to-senior FPGA/ASIC Design Engineer to join an advanced engineering team for national security applications. You will architect, design, implement, verify and integrate FPGA/ASIC systems, including cryptographic algorithms and high-speed protocols.

The role requires hands-on experience with VHDL, Xilinx Vivado, SystemVerilog, and UVM testbenches, plus strong verification and validation skills and C++ software-driven validation on Linux boards.

Qualifications

• 3+ years of experience implementing complex algorithms targeting FPGAs and/or ASICs.
• 5+ years of hands-on VHDL experience.
• Strong experience with Xilinx FPGA design and Vivado.

Responsibilities

• Develop architectures and implement high-throughput, complex FPGA/ASIC designs.
• Design and implement cryptographic algorithms using VHDL.
• Work with high-speed protocols including PCIe, NVMe, SR-IOV, 10G-400G Ethernet, and TCP/IP.
• Develop and integrate IP targeting ARM SoC FPGAs, including Xilinx MPSoC, and/or ASICs.
• Perform hands-on FPGA/ASIC architecture, design, verification, synthesis, and static timing analysis (STA).
• Develop and debug UVM-based testbenches and simulation sequences.
• Develop SystemVerilog Assertions (SVA) for verification.
• Develop and debug C++ software-driven validation on SoC evaluation boards running Linux.
• Support clock-domain crossing (CDC), lint, and reset-domain crossing (RDC) analysis.
• Work with modern FPGA/ASIC EDA tools and verification methodologies.

Skills

FPGA/ASIC design

VHDL

Xilinx Vivado

SystemVerilog

C++

UVM

Architecture

Verification & validation

Education

Bachelor’s degree in Electrical Engineering or Computer Science

Master’s degree in Electrical Engineering or Computer Science (plus)

Tools

Vivado

Mentor/Siemens EDA

Synopsys Design Compiler

PrimeTime

Questa

Job description

Entegee seeks a mid-to-senior FPGA/ASIC Design Engineer to join an advanced engineering team for national security applications. You will architect, design, implement, verify and integrate FPGA/ASIC systems, including cryptographic algorithms and high-speed protocols.

The role requires hands-on experience with VHDL, Xilinx Vivado, SystemVerilog, and UVM testbenches, plus strong verification and validation skills and C++ software-driven validation on Linux boards.