Senior FPGA/ASIC Design Engineer — Hybrid

Rolls-Royce; Reston (VA); Hybrid; USD 152,000 - 247,000; Full time

Benefits offered by this job

bonus

employee support assistance

employee discounts

base pay

discretionary bonus plan

health

dental

vision

disability

life and accidental death & dismemberm

flexible spending account

health savings account

401(k) retirement savings plan with a

Employee Assistance Program

Paid Time Off

certain paid holidays

paid parental and family care leave

tuition reimbursement

long-term incentive plan

Job summary

Rolls-Royce is seeking a Principal Engineer for FPGA/ASIC design in Reston, VA, with hybrid work and up to 25% travel to RR sites in Indiana. The role covers architecture, coding, verification, and certification documentation for engine control units.

You will develop RTL in VHDL/Verilog/SystemVerilog, run simulations, and drive timing closure while collaborating across global teams on flagship programs. A strong electronics background and US citizenship are required.

Qualifications

• Bachelor's degree in Electronics Engineering and/or Computer Engineering; 5+ years experience OR
• Master's degree in Electronics Engineering and/or Computer Engineering; 3+ years experience OR
• PhD in Electronics Engineering and/or Computer Engineering; U.S. Citizen required.

Responsibilities

• Participate in all phases of project; produce design docs, verification plans, and reports.
• Design and development of custom digital devices (ASIC/FPGA) for RR engine control units.
• Verify complex FPGA/ASIC products to DO-254 standards.
• Develop RTL using VHDL/Verilog/SystemVerilog; debug with simulations.
• Achieve timing closure on FPGA designs and generate test benches.
• Evaluate design flow: high-level design, synthesis, place-and-route, timing constraints, power.

Skills

FPGA design

ASIC design

RTL coding

VHDL/Verilog/SystemVerilog

timing closure

test benches

simulation

Do-254

Education

Bachelor's in Electronics/Computer Engineering

Master's in Electronics/Computer Engineering

PhD in Electronics/Computer Engineering

Tools

Xilinx tool flows

Actel tools

Cameo Systems Modeler (MagicDraw)

Git/SVN

MATLAB/Simulink

Job description

Rolls-Royce is seeking a Principal Engineer for FPGA/ASIC design in Reston, VA, with hybrid work and up to 25% travel to RR sites in Indiana. The role covers architecture, coding, verification, and certification documentation for engine control units.

You will develop RTL in VHDL/Verilog/SystemVerilog, run simulations, and drive timing closure while collaborating across global teams on flagship programs. A strong electronics background and US citizenship are required.