Senior FPGA/ASIC Electrical Engineer – Avionics

Prattwhitney; Melbourne (FL); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Three weeks of vacation

401(k) with employer matching

Tuition reimbursement

Student Loan Repayment Program

Life insurance and disability coverage

Parental leave benefits

Wellness programs

Employee Assistance Plan

Job summary

Pratt & Whitney seeks an experienced ASIC/FPGA design engineer to drive digital architecture, RTL development, and verification for airborne hardware. You will create RTL in VHDL/Verilog/SystemVerilog, build verification testbenches, and craft timing constraints while collaborating with cross‑functional teams on instrumented projects.

You will exploit FPGA toolchains (Questasim, Vivado, Libero, Synplify Pro), perform synthesis, timing analysis, and carry out DO-254 processes for AEH

Qualifications

• Typically requires a STEM degree with 5+ years of relevant experience or an advanced degree with 3+ years.
• Experience writing RTL and test benches using VHDL, Verilog, or SystemVerilog.
• Experience with FPGA tools (Questasim, Vivado, Libero, Synplify Pro).
• Experience with data interfaces (PCIe, DDR, I2C, Ethernet, ARINC-429).
• Experience with Linux and scripting languages (Python, Perl, etc.).

Responsibilities

• Requirements capture, decomposition, and traceability.
• ASIC/FPGA/MPSoC digital architecture development and design.
• Develop RTL design code and simulation in VHDL, Verilog, and SystemVerilog.
• Create verification testbenches using VHDL or UVM in SystemVerilog.
• Create timing constraints and perform synthesis, place & route.
• Conduct static timing analysis, linting, and clock-domain-crossing analysis.
• Perform ASIC/FPGA/SoC verification using inspection, simulation, and testing.
• Produce DO-254 DAL artifacts for AEH and participate in FAA audits.
• Mentor engineers and communicate with stakeholders across disciplines.
• Travel up to 10%.

Skills

RTL design

VHDL

Verilog

SystemVerilog

FPGA design

C/C++

Python

Linux

Scripting

DO-254 processes

Education

STEM degree

Tools

Questasim

Vivado

Libero

Synplify Pro

Job description

Pratt & Whitney seeks an experienced ASIC/FPGA design engineer to drive digital architecture, RTL development, and verification for airborne hardware. You will create RTL in VHDL/Verilog/SystemVerilog, build verification testbenches, and craft timing constraints while collaborating with cross‑functional teams on instrumented projects.

You will exploit FPGA toolchains (Questasim, Vivado, Libero, Synplify Pro), perform synthesis, timing analysis, and carry out DO-254 processes for AEH