Senior FPGA Architect: Lead High-Perf Compute

Teradyne; Reading (MA); Hybrid; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health and well-being benefits

Tuition assistance programs

Paid vacation & holidays

Job summary

Teradyne seeks a Senior FPGA Architect to architect and deliver high-performance FPGA-based solutions within the Compute Test division, based in North Reading, MA. The role combines FPGA design, board-level hardware, and system architecture across demanding interfaces and timing constraints.

You will lead architecture, collaborate across hardware, software, and verification teams, and mentor engineers while shaping robust test platforms for next-generation silicon and AI systems.

Qualifications

• 8+ years of hands-on FPGA design and development.
• Deep expertise in Verilog/SystemVerilog for design and debugging.
• Experience with PCIe, DDR, SerDes or similar high-speed interfaces.

Responsibilities

• Lead FPGA design from architecture through implementation and bring-up.
• Develop high-performance FPGA solutions with complex interfaces and subsystem integration.
• Collaborate with hardware, software, systems, and design verification teams to deliver cohesive system-level solutions.
• Build and execute validation strategies, including lab bring-up, debug, and root cause analysis using JTAG and lab instrumentation.
• Partner on PCB and system design decisions that affect FPGA performance and integration.
• Mentor junior engineers and serve as the technical lead for FPGA project teams.

Skills

FPGA design

Verilog/SystemVerilog

TCL

Python

High-speed interfaces

Tools

AMD Xilinx toolchains

Intel FPGA toolchains

Lab instrumentation

Job description

Teradyne seeks a Senior FPGA Architect to architect and deliver high-performance FPGA-based solutions within the Compute Test division, based in North Reading, MA. The role combines FPGA design, board-level hardware, and system architecture across demanding interfaces and timing constraints.

You will lead architecture, collaborate across hardware, software, and verification teams, and mentor engineers while shaping robust test platforms for next-generation silicon and AI systems.