Senior Formal Verification Engineer, SoC Security & IPs

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 150,000; Full time

Job summary

A leading technology company located in Beaverton, Oregon is looking for a Formal Verification Engineer with a minimum of 10 years of relevant experience in silicon validation. The candidate will be engaged in developing formal verification specifications and conducting security verification tasks for complex micro-architectures. This role requires hands-on experience with digital logic design and verification techniques, as well as proficiency in scripting languages. A commitment to inclusion and diversity is emphasized, with ongoing applications accepted.

Qualifications

• Minimum of 10 years of industry experience in silicon validation software engineering.
• Hands-on experience with formal methods and their applications.
• Knowledge of temporal logic assertion-based languages such as SVA or PSL.

Responsibilities

• Develop a formal micro-architecture specification.
• Create formal verification test plans including unique security requirements.
• Prove properties of designs and identify bugs.

Skills

VLSI and digital logic design knowledge

Scripting languages proficiency

Excellent debugging skills

Interpersonal skills

Knowledge of hardware specifications interpretation

Education

BS degree in related field

Tools

EDA formal tools

Job description

A leading technology company located in Beaverton, Oregon is looking for a Formal Verification Engineer with a minimum of 10 years of relevant experience in silicon validation. The candidate will be engaged in developing formal verification specifications and conducting security verification tasks for complex micro-architectures. This role requires hands-on experience with digital logic design and verification techniques, as well as proficiency in scripting languages. A commitment to inclusion and diversity is emphasized, with ongoing applications accepted.