Formal Verification Engineer for SoCs & IP

Apple, Inc.; Cupertino (CA); On-site; USD 174,000 - 225,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock programs

Relocation assistance

Tuition reimbursement

Job summary

Apple Inc. in Cupertino, California, seeks a hardware formal verification engineer to verify blocks and SOC IPs using model checking and HDL-based test benches. You will develop verification plans, prove properties, and collaborate with design teams to improve micro-architectures.

The role involves crafting reusable verification models and methodologies to boost efficiency, with a base pay range reflecting location and experience. Relocation and benefits may apply.

Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering, or related field.
• Experience with digital hardware design principles.
• Experience and/or education with model checking-based verification of hardware or protocols.
• Ability to communicate formal verification plans and results with validation and design partners.
• Analysis of computer architecture and SoCs.
• HDL knowledge including Verilog or VHDL; ability to develop formal test benches.
• Scripting languages including Python, Perl, or TCL in hardware CAD contexts.

Responsibilities

• Work on complete formal verification for CPU, Cellular and IP blocks and SOC components.
• Develop formal verification test plans and microarchitecture specifications.
• Prove properties, find design bugs, and collaborate with design teams to improve architectures.
• Create reusable and optimized formal models and verification code bases.
• Architect correct-by-construction design methodologies to improve verification efficiency and productivity.

Skills

Digital hardware design

Model checking

Verilog/VHDL

Python/Perl/TCL scripting

Communication of verification plans

Education

Bachelor's degree in Computer/Electrical/Electronics Engineering

Tools

Verilog

VHDL

Python

Perl

TCL

Job description

Apple Inc. in Cupertino, California, seeks a hardware formal verification engineer to verify blocks and SOC IPs using model checking and HDL-based test benches. You will develop verification plans, prove properties, and collaborate with design teams to improve micro-architectures.

The role involves crafting reusable verification models and methodologies to boost efficiency, with a base pay range reflecting location and experience. Relocation and benefits may apply.