Design Verification Engineer - SoC

Etched; San Jose (CA); On-site; USD 150,000 - 275,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving medical benefits

Housing subsidy of $2k per month

Relocation support to San Jose

Wellness benefits

Daily lunch and dinner in office

Job summary

A leading AI hardware firm is seeking a Design Verification Engineer to join their Systems/Performance Verification team. The role involves verifying custom IPs for robust and silicon-ready performance, closely collaborating with architects and software teams. Candidates should have strong knowledge in digital design, performance verification, and be skilled in SystemVerilog and Python. The company offers competitive compensation, generous benefits including medical coverage and relocation assistance, with an emphasis on in-person collaboration in San Jose.

Qualifications

• Experience in ASIC/SoC design and verification.
• Hands-on experience with performance verification and simulation.
• Expertise in SystemVerilog and Python for automation.

Responsibilities

• Verify performance features of ASIC design.
• Identify performance bottlenecks and tune software.
• Develop tests and coverage monitors in SystemVerilog and Python.
• Conduct performance tuning on silicon.

Skills

Digital design understanding

Performance verification

Automation with Python

SystemVerilog proficiency

Job description

Overview

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Responsibilities

• As a DV Engineer (Systems/Performance) owning the verification of a certain area of performance features in an ASIC design, you will have responsibilities as follows.
• Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
• Work closely with software and application developers on identifying performance bottlenecks and tuning the software.
• Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.
• Improve and maintain the architectural performance models.
• Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.
• Develop SystemVerilog or Python-based checkers for verifying the performance features.
• Develop coverage monitors and analyze coverage to ensure all performance features are covered.
• Debug performance issues and conduct performance tuning on silicon.
• Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

You may be a good fit if you have

• ASIC/SoC Design & Verification Experience: Strong understanding of digital design, RTL, and ASIC design flows.
• Hands-on experience with performance verification, simulation, and modeling.

SystemVerilog & Python Expertise

• Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
• Skilled in writing Python scripts for automation, data analysis, and performance modeling.

Architecture & Performance Modeling Knowledge

• Experience building and maintaining performance models for chip subsystems.
• Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.

Software Performance Profiling

• Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning.
• Some exposure to kernel level performance metrics and profiling tools.

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office

How We’re Different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Compensation Range: $150K - $275K