Senior FEOL/MOL Integration Engineer – Lead Cross-BU

Tokyo Electron; New York (NY); On-site; USD 148,000 - 209,000; Full time

Job summary

Tokyo Electron seeks a Principal FEOL/MOL integration Engineer to drive process integration across litho, etch, films, wets and CMP, defining new routes and leading wafer‑level execution in a senior IC role. You will own e-test capability, manage cross-BU projects, and mentor a team through data-driven optimization, DOE design, and rigorous quality control in a cleanroom environment.

The role requires a master’s or PhD with 8+ years in semiconductor integration, U.S.

Qualifications

• Master's degree or PhD with semiconductor experience, or a Bachelor's with 10+ years in the field.
• Semiconductor integration experience across litho, etch, films, wets, CMP required/beneficial.
• Principal/senior IC contributor with multi-stakeholder program experience preferred.
• U.S. work authorization required.

Responsibilities

• Serve as the principal technical authority for FEOL/MOL integration and mentor others.
• Define and build new process integration routes across litho, etch, films, wets, CMP.
• Establish and own e-test capability: test structure design, PCM, wafer-level parametrics.
• Lead cross-business-unit projects coordinating roadmaps, tool capabilities, and deliverables.
• Design, execute, and demonstrate proposed integration solutions on TEL vehicles with stats.
• Own lot management including splits, DOEs, metrology setup, and data evaluation.
• Support stakeholders in resolving integration issues through TEL equipment capability.

Skills

FEOL/MOL integration

Electrical test / parametric test

Cross-functional leadership

Metrology & analysis tools

DOE design & data analysis

Strong communication

Self-management & teamwork

Windows & MS Office

Education

Master's degree in Electrical Engineering or related field

PhD with experience

Bachelor's degree with 10+ years experience

Tools

SIVIEW MM/SM

JMP

Quartz PCI

MS Excel

Job description

Tokyo Electron seeks a Principal FEOL/MOL integration Engineer to drive process integration across litho, etch, films, wets and CMP, defining new routes and leading wafer‑level execution in a senior IC role. You will own e-test capability, manage cross-BU projects, and mentor a team through data-driven optimization, DOE design, and rigorous quality control in a cleanroom environment.

The role requires a master’s or PhD with 8+ years in semiconductor integration, U.S.