ASIC Verification Engineer – SoC & Memory

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 219,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA Corporation in Santa Clara, CA, seeks an ASIC Verification Engineer to verify design and implementation of leading SoCs and GPUs, collaborating with global teams to push verification methodologies and memory subsystem verification.

Requires a degree in EE/CS/CE and 2+ years of experience, strong SystemVerilog/UVM skills, C++, and experience with VCS or equivalent tools; equity eligibility and comprehensive benefits accompany the role.

Qualifications

• Requires a Bachelors or Masters in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
• 2+ years of relevant work or research experience.
• Strong history of verification methodology and reusable components.
• Knowledge of verification using random stimulus with functional coverage and assertion-based methods.
• Fluency in Object Oriented Programming with C++ and/or SystemVerilog.
• Exposure to design and verification tools (VCS) and debugging tools (Debussy, GDB) and methodologies (UVM).
• Strong communication skills are required.

Responsibilities

• Verify the design, architecture and micro-architecture using advanced verification methodologies.
• Define the verification scope and contribute to the verification infrastructure for memory subsystem units.
• Collaborate with architects, designers and software engineers across sites to achieve goals.

Skills

UVM / SystemVerilog

C++

Debugging

Verifications methodologies

Communication

Education

Bachelor's or Master's in EE/CS/CE

Equivalent experience

Tools

VCS

Debussy

GDB

Verilog/SystemVerilog

UVM

Job description

NVIDIA Corporation in Santa Clara, CA, seeks an ASIC Verification Engineer to verify design and implementation of leading SoCs and GPUs, collaborating with global teams to push verification methodologies and memory subsystem verification.

Requires a degree in EE/CS/CE and 2+ years of experience, strong SystemVerilog/UVM skills, C++, and experience with VCS or equivalent tools; equity eligibility and comprehensive benefits accompany the role.