Senior ESD/Latch-Up Architect - HBM & 3D IC

Micron Memory Malaysia Sdn Bhd; Folsom (CA); On-site; USD 177,000 - 334,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Paid time off

Job summary

Micron Technology is seeking a Sr. Member Technical Staff to define end-to-end ESD/Latch-Up architectures for HBMs, across base dies, DRAM stacks, and interconnects.

The role drives protection strategies for high-speed I/O and TSV interfaces, and establishes standards and signoff criteria with cross-functional teams. You will collaborate with foundry and packaging teams to address complex system-level ESD challenges and ensure robust reliability from architecture through silicon validation.

Qualifications

• MS/PhD in Electrical Engineering or related field, or equivalent practical experience.
• 10+ years in ESD and latch-up design and reliability.
• Experience with advanced CMOS (FinFET/GAA) and 3D stacking.
• Ability to work across cross-functional teams.

Responsibilities

• Define end-to-end ESD and latch-up architecture across base die, DRAM stacks, and interconnects.
• Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging.
• Establish ESD/LUP standards, rule decks, and signoff criteria.
• Drive correlation between design assumptions, silicon validation, and field reliability.
• Partner with foundry and packaging teams on system-level ESD challenges.

Skills

ESD/Latch-up design

CMOS technologies

3D IC/TSV interfaces

Reliability engineering

PDK/Rule decks

Education

MS or PhD in Electrical Engineering

Tools

EDA tools

PDK collateral

Job description

Micron Technology is seeking a Sr. Member Technical Staff to define end-to-end ESD/Latch-Up architectures for HBMs, across base dies, DRAM stacks, and interconnects.

The role drives protection strategies for high-speed I/O and TSV interfaces, and establishes standards and signoff criteria with cross-functional teams. You will collaborate with foundry and packaging teams to address complex system-level ESD challenges and ensure robust reliability from architecture through silicon validation.