Sr. Member Technical Staff - ESD and Latch-Up - HBM

Micron Technology; Folsom (CA); On-site; USD 177,000 - 334,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time‑off program

Job summary

Micron Technology is looking for a Senior Engineer as an SMTS/DMTS HBM ESD/Latch‑Up Architect to lead the definition of ESD and latch‑up architecture across various components. The ideal candidate will have over 10 years of experience and a strong background in advanced CMOS technologies.

The role includes developing protection strategies and collaborating with cross‑functional teams. Compensation ranges from $177,000 to $334,000 per year, in addition to various benefits tailored to meet healthcare needs.

Qualifications

• 10+ years of experience in ESD and latch‑up design and reliability.
• Expertise in advanced CMOS technologies such as FinFET or GAA.
• Experience with 3D IC, TSV, or die‑to‑die interfaces.

Responsibilities

• Define end-to-end ESD and latch‑up architecture across base die, DRAM die, and interconnects.
• Develop protection strategies for high‑speed I/O, TSV interfaces, and advanced packaging.
• Drive correlation between design assumptions, silicon validation, and field reliability.

Skills

ESD and latch‑up design

Advanced CMOS technologies

Technical leadership

Education

MS or PhD in Electrical Engineering or related field

Job description

SMTS/DMTS HBM ESD/Latch‑Up Architect – Micron Technology

Micron Technology invites a Senior Engineer to define protection strategies across base die, DRAM stacks, and interconnects, shaping product reliability from early architecture through silicon validation. The role involves influencing technical direction and solving system‑level ESD challenges across cross‑functional teams.

Responsibilities

• Define end-to-end ESD and latch‑up architecture across base die, DRAM die, and interconnects
• Develop protection strategies for high‑speed I/O, TSV interfaces, and advanced packaging
• Establish ESD/LUP standards, rule decks, and signoff criteria
• Drive correlation between design assumptions, silicon validation, and field reliability
• Partner with foundry and packaging teams on system‑level ESD challenges

Minimum Qualifications

• MS or PhD in Electrical Engineering or related field, or equivalent practical experience
• 10+ years of experience in ESD and latch‑up design and reliability
• Expertise in advanced CMOS technologies such as FinFET or GAA
• Experience with 3D IC, TSV, or die‑to‑die interfaces

Preferred Qualifications

• Experience defining architecture across multi‑die or stacked memory systems
• Background in ESD device or circuit design
• Experience developing PDK collateral or ESD rule decks
• Experience debugging silicon failures related to ESD or latch‑up
• Demonstrated technical leadership across cross‑functional teams

Compensation

The US base salary range for this full‑time position is $177,000.00 – $334,000.00 per year. Additional compensation may include bonuses and equity.

The salary range reflects the minimum and maximum target base pay for new hires across all US locations. Individual pay is determined by work location and other factors such as knowledge, skills, experience, tenure, and relevant education or training. The pay scale is subject to change based on business needs.

Benefits

Micron offers medical, dental, and vision plans in all locations, allowing team members to choose plans that best meet family healthcare needs and budget. Benefit programs protect income if you are unable to work due to illness or injury, and include paid family leave, a robust paid time‑off program, and paid holidays. For additional information regarding benefit programs, see the Benefits Guide posted on micron.com/careers/benefits.

Equal Opportunity Employment

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.