Senior Embedded Memory Tech Lead - ReRAM

onsemi; Gresham (OR); On-site; USD 140,000 - 190,000; Full time

Job summary

onsemi is seeking a senior technical professional to join the IC Technology Development organization and help define next-generation embedded memory technologies. The successful candidate will provide technical leadership across memory bitcell development, process integration, silicon characterization, reliability qualification, and reusable memory IP enablement.

This role operates in a cross-functional Memory Center of Excellence, partnering with device engineering, process integration, circuit

Qualifications

• Master of Science or Ph.D. in Electrical Engineering, Materials Science, Physics, Semiconductor Engineering, or a related technical discipline.
• 5-10 years of relevant semiconductor industry experience in technology development, process integration, device engineering, characterization, reliability, or memory development.
• Strong understanding of semiconductor devices, wafer fabrication, process integration, and electrical characterization methodologies.
• Experience planning and analyzing DOE/split experiments, silicon learning vehicles, statistical data sets, yield learning, or technology qualification data.
• Knowledge of memory characterization methods including read, write, retention, endurance, variability, margin, and failure-mode evaluation.
• Working knowledge of device modeling, compact model correlation, SPICE/TCAD simulation concepts, or circuit-to-silicon correlation.
• Familiarity with semiconductor reliability principles and qualification methodologies such as HTOL, retention, endurance, ESD, latch-up, and failure analysis.
• Demonstrated ability to lead complex cross-functional engineering efforts from concept through silicon learning and qualification readiness.
• Excellent written and verbal communication skills with ability to present technical recommendations, risks, and tradeoffs to cross-functional teams.

Responsibilities

• Lead development of advanced embedded memory technologies with emphasis on ReRAM and other emerging non-volatile memory solutions.
• Define memory technology requirements including PPA targets, density goals, endurance, retention, cost, yield, and manufacturability criteria.
• Drive bitcell and array architecture evaluations, including topology selection, assist schemes, variability assessment, margin analysis, and DFM assumptions.
• Plan and execute silicon learning activities, including test-chip definition, split/DOE planning, metrology, electrical characterization, and data analysis.
• Analyze read/write behavior, endurance, retention, disturb mechanisms, variation, failure Pareto trends, and model-to-silicon correlation.
• Partner with process integration and module teams to align FEOL/BEOL process modules, integration assumptions, and manufacturing readiness.
• Translate silicon learning into design rules, compact models, memory assumptions, characterization specifications, and reusable technology collateral.
• Support memory IP development including periphery assumptions, compiler needs, verification criteria, release checklist, and sign-off constraints.
• Define reliability stress plans, qualification gates, activation energy assumptions, failure-mode investigations, and risk register updates
• Lead cross-functional technical reviews, roadmap discussions, risk escalations, decision gates, and action closure across memory development workstreams.
• Mentor engineers and communicate complex technical tradeoffs clearly to design, product, manufacturing, quality, and leadership stakeholders.

Skills

Technical leadership

Cross-functional collaboration

DOE planning

Memory technology knowledge

Reliability planning

Education

Master of Science or Ph.D. in Electrical Engineering or related

Tools

SPICE/TCAD

Circuit-to-silicon correlation

Job description

onsemi is seeking a senior technical professional to join the IC Technology Development organization and help define next-generation embedded memory technologies. The successful candidate will provide technical leadership across memory bitcell development, process integration, silicon characterization, reliability qualification, and reusable memory IP enablement.

This role operates in a cross-functional Memory Center of Excellence, partnering with device engineering, process integration, circuit