Senior Design Verification Engineer (Space)

Viasat; Tempe (AZ); On-site; USD 133,000 - 197,000; Full time

Job summary

Viasat is seeking a Senior Design Verification Engineer in the United States to lead RTL verification for FPGA and ASIC designs. You will create tests, develop SystemVerilog/UVM testbenches, and drive coverage and regressions with the RTL team.

You will evaluate tools like Questa, Xcelium and VCS, manage resources, and ensure timely delivery in a fast-paced, site-based environment. Travel up to 10% may be required.

Qualifications

• Bachelor's degree in electrical or computer engineering or related field.
• 5+ years of design verification experience including UVM testbench experience.
• Experience with digital logic and timing considerations.
• Proven ability to follow coding guidelines and participate in code reviews.
• Experience with Questa, Xcelium and VCS simulators.

Responsibilities

• Create drivers, monitors, scoreboards, sequences and model predictors for interfaces and designs.
• Maintain program schedule and task tracking using Agile Jira.
• Debug failing tests and collaborate with RTL developers.
• Run and analyze regressions.

Skills

SystemVerilog

UVM

Testbench development

Debugging

Coverage analysis

Agile Jira

RTL verification

Tool evaluation

License management

Education

Bachelor's Degree in Electrical Engineering

or Computer Engineering

Tools

Questa

Xcelium

VCS

Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

What you'll do

As a senior Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:

• Design verification planning including test plans
• Testbench development using SystemVerilog/UVM
• Hands-on debug with the design team
• Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
• Managing regressions and compute resources
• Tool evaluation and license management
• Responsible for owning and driving technical issues to resolution

You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.

At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.

This is a site‑based role, employees work 3+ days (60%+) per week from a Viasat office or work location within a standard five‑day workweek.

The day-to-day

• Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs
• Maintaining and communicating program schedule and task tracking (Agile Jira based)
• Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers
• Running and analyzing regressions

What you'll need

• Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
• 5+ years Design Verification experience including UVM testbench experience
• Foundational knowledge of digital logic and timing considerations
• Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
• Experience with industry standard simulators such as Questa, Xcelium, and VCS
• Proven track record of work in UVM testbench development
• Good oral and written communications skills
• US citizenship
• Ability to travel up to 10%

What will help you on the job

• Strong written and verbal communication skills, ability to work with a geographically distributed team
• Object oriented programming experience
• Familiarity with designing and coding for testbench horizontal and vertical re-use
• Ability to work independently, take initiative, and take ownership of tasks and results
• Familiarity with CI/CD practices
• Familiarity with AI Agents (Claud Code, Copilot, etc.)
• Strong troubleshooting skills

#LI-GS1

Salary range

$132,500.00 - $209,500.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $164,500.00- $246,500.00/ annually

At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat’s comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.

EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.