Lead Digital Verification Engineer – Space/ASIC (LEO)

E-Space; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Job summary

E-Space is looking for a Digital Design Verification Engineer to join their team in Saratoga, California. The ideal candidate will verify custom ASICs for satellite and wireless telephony, leveraging over 10 years of design verification experience in the semiconductor industry. Expertise in Verilog, SystemVerilog, and UVM is essential. This full-time position offers a target base pay of $120,000 – $220,000 annually, with significant opportunities to innovate in satellite technology. Come make a difference at E-Space.

Qualifications

• Expert-level proficiency in Verilog and SystemVerilog.
• Proven experience building UVM verification environments from scratch.
• Deep understanding of verification methodologies and best practices.

Responsibilities

• Verify custom ASICs for satellite and wireless telephony.
• Write comprehensive test plans and maintain test suites.
• Debug complex RTL simulations and gate-level simulations.

Skills

Verilog

SystemVerilog

UVM

C/C++ coding

Scripting skills in Perl or Python

Bash scripting

Education

10+ years of design verification experience in the semiconductor industry

Job description

E-Space is looking for a Digital Design Verification Engineer to join their team in Saratoga, California. The ideal candidate will verify custom ASICs for satellite and wireless telephony, leveraging over 10 years of design verification experience in the semiconductor industry. Expertise in Verilog, SystemVerilog, and UVM is essential. This full-time position offers a target base pay of $120,000 – $220,000 annually, with significant opportunities to innovate in satellite technology. Come make a difference at E-Space.