Senior DSP Engineer - Satellite Communications Payloads

ACL Digital

El Segundo (CA)

On-site

USD 134,000 - 191,000

Full time

4 days ago
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Job summary

ACL Digital in El Segundo, CA seeks a Senior/Lead DSP Algorithms Engineer to design, develop, and validate space-based satellite communication payloads. You will drive RF/digital system work from concept to in-orbit operations.

The role requires 5+ years in core DSP and digital communications, MATLAB/Simulink expertise, and HDL/FPGA/ASIC collaboration. On-site shift and U.S. residency are expected for defense programs.

Qualifications

  • 5+ years of core digital communications and signal processing theory (equalization, Turbo/Viterbi coding/decoding, channel estimation)
  • 3+ years with MATLAB or Simulink
  • 3+ years Systems Engineering: requirements, architecture, trade studies and verification
  • 1+ years Hardware Integration with FPGAs/ASICs
  • Must be a U.S. Person for export compliance

Responsibilities

  • Design and develop next-generation RF and digital satellite communication systems.
  • Develop, model, and verify multi-rate, fixed-point DSP algorithms.
  • Perform detailed trade studies, system design, performance analysis, and waveform characterization.
  • Support HDL-level design/verification and work with FPGAs or ASICs.
  • Assist in integration and testing of payloads and spacecraft from unit level through in-orbit deployment.
  • Lead engineering teams and IR&D initiatives.

Skills

DSP algorithms
Digital communications theory
Fixed-point DSP
System modeling
HDL integration awareness

Education

Bachelor of Science in Engineering or related technical field

Tools

MATLAB
Simulink
FPGA/ASIC knowledge

Job description

ACL Digital in El Segundo, CA seeks a Senior/Lead DSP Algorithms Engineer to design, develop, and validate space-based satellite communication payloads. You will drive RF/digital system work from concept to in-orbit operations.

The role requires 5+ years in core DSP and digital communications, MATLAB/Simulink expertise, and HDL/FPGA/ASIC collaboration. On-site shift and U.S. residency are expected for defense programs.

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