Senior DRAM Verification Engineer – Boise

Micron Memory Malaysia Sdn Bhd; Boise, Northern (ID, KY); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Career growth

Job summary

Micron Technology in Boise, Idaho is seeking an MTS Design Verification Engineer to lead DRAM verification for next‑generation memory products. You will shape verification strategy, guide methodologies, and collaborate with global teams to deliver high‑quality, scalable solutions. The role requires 8+ years in DRAM or CMOS verification, strong transistor‑level debugging, and experience with Verilog/SystemVerilog and HSPICE. Advanced degree and Python skills with AI-assisted tools are a plus.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience in DRAM/memory or advanced CMOS verification.
• Strong circuit analysis and debugging at the transistor level.

Responsibilities

• Lead DRAM verification innovation, driving key technical decisions, architecture, and strategy during product execution.
• Collaborate with global teams to define and implement best-known methods for verification and product development.
• Drive verification planning, coverage closure, and silicon debugging for advanced DRAM products.
• Evaluate and implement new tools, methodologies, and flows to improve verification efficiency and quality.
• Mentor engineers and provide technical leadership while contributing expert guidance to senior leadership teams.

Skills

DRAM verification

Circuit analysis

Debug skills

Verilog/SystemVerilog

HSPICE/FINESIM

Python

Leadership

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Tools

UVM

Mixed-signal verification

DDR5

Job description

Micron Technology in Boise, Idaho is seeking an MTS Design Verification Engineer to lead DRAM verification for next‑generation memory products. You will shape verification strategy, guide methodologies, and collaborate with global teams to deliver high‑quality, scalable solutions. The role requires 8+ years in DRAM or CMOS verification, strong transistor‑level debugging, and experience with Verilog/SystemVerilog and HSPICE. Advanced degree and Python skills with AI-assisted tools are a plus.