Staff DRAM Verification Engineer — Innovate Memory

Micron Technology, Inc; Boise (ID); On-site; USD 105,000 - 140,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision plans

Paid time off

Holidays

Job summary

Micron Technology, Inc. in Boise, Idaho seeks a Staff Verification Design Engineer to shape verification strategies for DRAM products and collaborate across design, product engineering, test, and process integration to ensure performance and reliability.

The role emphasizes solving complex circuit and system-level challenges, with mentorship across global teams and hands-on verification of memory architectures using SPICE, Verilog, and industry tools.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or Computer Engineering.
• 5+ years of verification or related design experience.
• Strong background in semiconductor circuit design, modeling, and verification.
• Proficiency with HSPICE and Python.
• Knowledge of DRAM/memory architecture and verification challenges.

Responsibilities

• Contribute to the design and drive the verification of memory circuits from gate-level to full chip implementations.
• Develop and execute verification plans for advanced DRAM builds.
• Lead circuit- and system-level verification using industry-standard tools and methodologies.
• Drive verification of memory arrays, control logic, address decode, data paths, and internal test logic.
• Analyze layout-extracted parasitics and guide critical circuit reviews.

Skills

Verification experience

DRAM architecture

RTL verification

Python

HSPICE

Verilog

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

HSPICE

Python

Verilog

Job description

Micron Technology, Inc. in Boise, Idaho seeks a Staff Verification Design Engineer to shape verification strategies for DRAM products and collaborate across design, product engineering, test, and process integration to ensure performance and reliability.

The role emphasizes solving complex circuit and system-level challenges, with mentorship across global teams and hands-on verification of memory architectures using SPICE, Verilog, and industry tools.