Senior Wireless SoC Design Engineer (Low-Power)

Microchip Technology Inc

Chandler (AZ)

On-site

USD 91,000 - 232,000

Full time

14 days+

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Benefits offered by this job

Competitive base pay
Restricted stock units
Quarterly bonus payments
Health benefits starting day one
Retirement savings plans
Employee Stock Purchase Plan with a 2-year look back feature

Job summary

A leading semiconductor company in Arizona is looking for a Design Engineer to develop high-performance, low-power SOC solutions. This role involves collaborating with cross-functional teams to ensure quality product delivery. Ideal candidates should have at least 12 years of experience in digital SOC design and proficiency in RTL design, low-power techniques, and SOC architecture. You will actively contribute to SOC projects and participate in design evaluations. Competitive compensation package is offered, including health benefits from day one.

Qualifications

  • 12+ years of experience in digital SOC design, focusing on low-power design.
  • Experience with ASIC design flow including power estimations and low-power techniques.
  • Strong understanding of SOC architecture and bus protocols.

Responsibilities

  • Contribute to SOC design from concept to tape-out.
  • Implement SOC designs according to specifications, performing timing analysis.
  • Collaborate with verification teams to ensure thorough design verification.

Skills

RTL design (Verilog/System Verilog)
Low-power design
Problem solving
Communication skills

Education

Bachelor's degree in computer engineering, electrical engineering, or related field
Master's degree in related field (preferred)

Tools

TCL
Perl
Python

Job description

A leading semiconductor company in Arizona is looking for a Design Engineer to develop high-performance, low-power SOC solutions. This role involves collaborating with cross-functional teams to ensure quality product delivery. Ideal candidates should have at least 12 years of experience in digital SOC design and proficiency in RTL design, low-power techniques, and SOC architecture. You will actively contribute to SOC projects and participate in design evaluations. Competitive compensation package is offered, including health benefits from day one.
Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior Low-Power SoC/ASIC Design Engineer
Senior Low-Power SoC/ASIC Design Engineer

Qualcomm • Santa Clara (CA)

On-site
USD 176,300 - 264,500
Competitive salary
Annual discretionary bonus program
Annual RSU grants
Senior Digital SoC Designer - Wireless & Low-Power
Senior Digital SoC Designer - Wireless & Low-Power

Top Workforce Solutions, LLC • Chandler (AZ)

On-site
USD 123,000 - 168,000
Performance-based bonuses
Excellent benefits package
Up to 25% travel
Senior SoC Power Design Engineer (Low Power)
Senior SoC Power Design Engineer (Low Power)

Qualcomm • San Diego (CA)

On-site
USD 140,000 - 210,000
Senior Power Systems Engineer — Low-Power Chipsets
Senior Power Systems Engineer — Low-Power Chipsets

Qualcomm • Austin (TX)

On-site
USD 187,000 - 280,000
Senior ASIC Design Engineer - Low-Power SOC & WiFi
Senior ASIC Design Engineer - Low-Power SOC & WiFi

Anysilicon • Santa Clara (CA)

Hybrid
USD 120,000 - 150,000
Wireless PHY RTL Engineer: Low-Power SoC Design
Wireless PHY RTL Engineer: Low-Power SoC Design

Apple • Irvine (CA)

On-site
USD 139,500 - 258,100
Comprehensive medical and dental coverage
Retirement benefits
Educational reimbursement
Senior Wireless SoC Architect & RTL Engineer
Senior Wireless SoC Architect & RTL Engineer

Apple • San Diego (CA)

On-site
USD 171,600 - 302,200
Comprehensive medical coverage
Retirement benefits
Discounted products
Low-Power SOC Flow Engineer – AI/ML Driven
Low-Power SOC Flow Engineer – AI/ML Driven

Apple Inc. • Cupertino (CA)

On-site
USD 147,400 - 272,100
Comprehensive medical and dental coverage
Retirement benefits
Employee stock purchasing program
+2
Staff Digital Design Engineer: Low-Power SoC & Clocking
Staff Digital Design Engineer: Low-Power SoC & Clocking

Silicon Labs • Austin (TX)

On-site
USD 143,150 - 265,850
Great medical, dental, and vision plans
401k plan with match
Flexible PTO schedule
+2
Senior Digital SoC Design Engineer (DSP/RTL)
Senior Digital SoC Design Engineer (DSP/RTL)

Cirrus Logic • Chandler (AZ)

On-site
USD 100,000 - 130,000