Senior Digital Physical Design & Integration Engineer

Micron Technology; San Jose (CA); On-site; USD 145,000 - 246,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology in the United States seeks an experienced Design Engineer to design and analyze digital and analog circuits for memory products. You will own physical implementation, top-level integration, and partition-level flow from planning to hand-off, collaborating globally across design, verification, and manufacturing teams to optimize cost, quality, and reliability.

The role requires 5+ years in digital physical design, strong timing analysis (PrimeTime), and hands-on Cadence Innovus

Qualifications

• 5+ years of digital physical design with at least one full tapeout owned end-to-end.
• Strong static timing analysis and debug skills. Fluent with PrimeTime across MMMC and OCV/AOCV/POCV; able to dissect violations and differentiate issues from constraints.
• Hands-on expertise with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning — virtual flat, partitioning, pin optimization, budgeting, assembly.
• Proven experience with top-level digital integration flow end-to-end — driving a full-chip or large-partition design from planning through assembly and hand-off.
• Strong flat APR expertise with Innovus (or ICC2): floorplan, place, CTS, route, ECO, sign-off correlation.
• Synthesis proficiency with Design Compiler or Genus (WLM + topographical/physical); familiarity with MBFF, don't_touch, clock gating.
• Physical verification with Calibre: DRC, LVS, antenna; hierarchical vs. flat runs and waiver management.
• SDC authoring for multi-mode/multi-corner designs; derive and validate budgets from top-level planning.

Responsibilities

• Contribute to development of new product opportunities by designing, laying out, and optimizing Memory/Logic/Analog circuits.
• Lead parasitic modeling and assist in design validation, tape-out revisions.
• Oversee layout process: floorplanning, placement, routing; drive top-level integration.
• Perform verification with modeling and simulation using industry-standard tools.
• Collaborate with Marketing, Probe, Process, Test, and Product Engineering to ensure manufacturability.
• Mentor engineers in CAD, modeling, and verification to improve design quality.
• Pioneer innovative approaches for future Memory generations in a dynamic team.

Skills

Digital design

Physical design

Timing analysis

Cadence Innovus

ICC2

PrimeTime

Tcl scripting

Python

Synthesis

Layout optimization

Education

Bachelor’s degree in Computer Engineering or Electrical Engineering

Tools

Cadence Innovus

ICC2

Calibre

Design Compiler

Genus

Job description

Micron Technology in the United States seeks an experienced Design Engineer to design and analyze digital and analog circuits for memory products. You will own physical implementation, top-level integration, and partition-level flow from planning to hand-off, collaborating globally across design, verification, and manufacturing teams to optimize cost, quality, and reliability.

The role requires 5+ years in digital physical design, strong timing analysis (PrimeTime), and hands-on Cadence Innovus