Digital Design Verification Engineer

EF; Austin (TX); On-site; USD 130,000 - 210,000; Full time

Benefits offered by this job

Equity & Ownership

Proximity Bonus (Living-Local)

Retirement Benefits

Job summary

OLIX in Austin is seeking Senior/Staff Digital Verification Engineers to own verification of high-speed data-processing silicon. You will drive end-to-end verification from algorithms to RTL and bring-up, using SystemVerilog/UVM, formal methods, and Python/MATLAB toolchains.

Ideal candidates have 5+ years in ASIC/SoC verification, experience with GHz-class designs, and strong collaboration across digital, optical, and software teams.

Qualifications

• 5+ years of hands-on digital verification experience in high‑performance ASICs or SoCs.
• Ownership of verification for at least one complex block or subsystem processing continuous real‑time data streams.
• Proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (UVM, CocoTB).
• Experience with GHz clock domains, CDC/RDC analysis, and RTL/formal verification flows.

Responsibilities

• Own end-to-end verification of high-throughput digital pipelines for multi-GSPS input rates.
• Develop and maintain verification environments using SystemVerilog/UVM with constrained-random testing and coverage closure.
• Define and implement assertion-based strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.
• Apply formal verification techniques to complement simulation and accelerate bug discovery.
• Model and validate algorithms in MATLAB/Simulink or Python, ensuring equivalence from models to RTL and gate-level sign-off.
• Support FPGA prototyping and silicon bring-up with targeted testcases and debug strategies.
• Collaborate across digital, optical, mixed-signal and software teams for correct integration.
• Analyze verification results to identify root causes and drive design fixes to improve efficiency.
• Contribute to verification methodology, documentation, and reviews; mentor junior engineers.

Skills

Digital verification

SystemVerilog/UVM

GHz-class clock domain verification

Formal verification techniques

Python/NumPy modelling

Tools

SystemVerilog

UVM

CocoTB

MATLAB/Simulink

Python

Job description

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

The Role

We are seeking highly skilled and motivated Senior / Staff Digital Verification Engineers with a strong background in CMOS digital design and verification to take ownership of the functional correctness of high-speed, real-time data-processing silicon, from early algorithm modelling through verified RTL, sign-off, and silicon bring-up.

You will join a multidisciplinary group creating groundbreaking hardware where digital, optical, and mixed-signal domains intersect.

The ideal candidate brings deep expertise in digital verification methodologies, a solid understanding of hardware architecture, and a passion for building provably correct, high-performance systems that underpin breakthrough AI hardware.

Responsibilities

• Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes
• Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation
• Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance
• Apply formal verification techniques (property checking, assertions, equivalence checking) to complement simulation-based verification and accelerate bug discovery
• Model and validate algorithms using MATLAB/Simulink or Python, ensuring functional equivalence from algorithmic models through RTL and gate-level sign-off
• Support FPGA prototyping and silicon bring-up by developing targeted testcases, debug strategies, and post-silicon validation plans
• Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions
• Analyse verification results to identify root causes, drive design fixes, and improve verification efficiency and reuse
• Contribute to verification methodology development, documentation, and design/verification reviews; mentor junior engineers where appropriate

Skills & Experience

• 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs
• Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams
• Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM. CocoTB)
• Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis
• Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation
• Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces
• Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation
• Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics
• Clear communicator who collaborates effectively across disciplines and is comfortable operating in a fast-moving, evolving environment

Nice to have

• Tape-out experience on an advanced process node
• Deep hands-on experience with formal verification methodologies, including property decomposition, and coverage-driven formal on tools such as Jasper
• Exposure to coherent optical links or photonic-electronic co-design
• Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures
• Expertise in arithmetic pipeline verification
• Expertise in processor and ISA verification
• Contributions to open-source RTL, verification frameworks, or FPGA platforms

Compensation & Equity

• Competitive Salary: Commensurate with your experience, skills, and location
• Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it
• Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
• Retirement Benefits:Employer-contributed retirement plans to help you build long-term financial security.
  

Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.